NXP Semiconductors KE1xF Series, Reference Manual, Page: 1403 / 1483

1. RTR bit of the Incoming Frame. It is saved into an auxiliary MB called Rx Serial Message Buffer (Rx SMB).
2. If the CTRL2[EACEN] bit is negated, the RTR bit of Mailbox is never compared with the RTR bit of the incoming frame.
3. If the CAN_CTRL2[EACEN] bit is negated, the IDE bit of Mailbox is always compared with the IDE bit of the incoming
frame.
50.4.6 Rx 14 Mask register (CANx_RX14MASK)
This register is located in RAM.
RX14MASK is provided for legacy application support. When the CAN_MCR[IRMQ]
bit is asserted, RX14MASK has no effect.
RX14MASK is used to mask the filter fields of Message Buffer 14.
This register can only be programmed while the module is in Freeze mode as it is blocked
by hardware in other modes.
Address: Base a 14h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
RX14M
W
Reset
x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x*
* Notes:
x = Undefined at reset. •
CANx_RX14MASK field descriptions
Field Description
RX14M Rx Buffer 14 Mask Bits
Each mask bit masks the corresponding Mailbox 14 filter field in the same way that RXMGMASK masks
other Mailboxes' filters. See the description of the CAN_RXMGMASK register.
0 The corresponding bit in the filter is "don’t care."
1 The corresponding bit in the filter is checked.
50.4.7 Rx 15 Mask register (CANx_RX15MASK)
This register is located in RAM.
RX15MASK is provided for legacy application support. When the CAN_MCR[IRMQ]
bit is asserted, RX15MASK has no effect.
RX15MASK is used to mask the filter fields of Message Buffer 15.
This register can be programmed only while the module is in Freeze mode because it is
blocked by hardware in other modes.
Chapter 50 CAN (FlexCAN)
Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019
NXP Semiconductors 1403