NXP Semiconductors KE1xF Series, Reference Manual, Page: 454 / 1483

SCG_CSR field descriptions (continued)
Field Description
1010 Divide-by-11
1011 Divide-by-12
1100 Divide-by-13
1101 Divide-by-14
1110 Divide-by-15
1111 Divide-by-16
DIVSLOW Slow Clock Divide Ratio
0000 Reserved
0001 Divide-by-2
0010 Divide-by-3
0011 Divide-by-4
0100 Divide-by-5
0101 Divide-by-6
0110 Divide-by-7
0111 Divide-by-8
1000 Reserved
1001 Reserved
1010 Reserved
1011 Reserved
1100 Reserved
1101 Reserved
1110 Reserved
1111 Reserved
19.3.4 Run Clock Control Register (SCG_RCCR)
This register controls the system clock source and the system clock dividers for the core,
platform, external and bus clock domains when in Run mode only. This register can only
be written using a 32-bit write. Selecting a different clock source when in RUN requires
that clock source to be enabled first and be valid before system clocks switch to that
clock source. If system clock divide ratios also change when selecting a different clock
mode when in RUN, new system clock divide ratios will not take affect until new clock
source is valid.
Address: 4006_4000h base + 14h offset = 4006_4014h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
SCS
0
DIVCORE Reserved
0
DIVBUS DIVSLOW
W
Reset
0 0 0 0 0 0 1 1 0 0 0 0 * * * * 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
* Notes:
DIVCORE field: The reset value is controlled by user FOPT bits that get uploaded during reset. The two valid reset values
are div-by-1 and div-by-2
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Memory Map/Register Definition
Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019
454 NXP Semiconductors