NXP Semiconductors KE1xF Series, Reference Manual, Page: 451 / 1483

SCG memory map (continued)
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4006_4600 System PLL Control Status Register (SCG_SPLLCSR) 32 R/W 0000_0000h 19.3.19/476
4006_4604 System PLL Divide Register (SCG_SPLLDIV) 32 R/W 0000_0000h 19.3.20/478
4006_4608 System PLL Configuration Register (SCG_SPLLCFG) 32 R/W 0000_0000h 19.3.21/479
19.3.1 Version ID Register (SCG_VERID)
Note: Writing to this register will result in a transfer error.
Address: 4006_4000h base + 0h offset = 4006_4000h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
VERSION
W
Reset
0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SCG_VERID field descriptions
Field Description
VERSION SCG Version Number
19.3.2 Parameter Register (SCG_PARAM)
Note: Writing to this register will result in a transfer error.
Address: 4006_4000h base + 4h offset = 4006_4004h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
DIVPRES 0 0 CLKPRES
W
Reset
* * * * * 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * * * * * * * *
* Notes:
DIVPRES field: The reset value is controlled by which SCG System Dividers are used by Soc. •
CLKPRES field: The reset value is controlled by which SCG Clock Sources are used by Soc. Please reference the
Reference manual clocking chapter.
•
SCG_PARAM field descriptions
Field Description
31–27
DIVPRES
Divider Present
Indicates which system clock dividers are present in this instance of SCG.
Table continues on the next page...
Chapter 19 System Clock Generator (SCG)
Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019
NXP Semiconductors 451