NXP Semiconductors KE1xF Series, Reference Manual, Page: 476 / 1483

19.3.19 System PLL Control Status Register (SCG_SPLLCSR)
Address: 4006_4000h base + 600h offset = 4006_4600h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
SPLLERR
SPLLSEL
SPLLVLD
LK
0
SPLLCMRE
SPLLCM
W
w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
SPLLSTEN
SPLLEN
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SCG_SPLLCSR field descriptions
Field Description
31–27
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
26
SPLLERR
System PLL Clock Error
This flag is reset on Chip POR only, software can also clear this flag by writing a logic one
NOTE: The LOL Flag is set when the PLL reference is out of range (Dunl in datasheet) and is constantly
modulated such that 3 consecutive un-locked samples of the reference clock are generated.
0 System PLL Clock Monitor is disabled or has not detected an error
1 System PLL Clock Monitor is enabled and detected an error. System PLL Clock Error flag will not set
when System OSC is selected as its source and SOSCERR has set.
25
SPLLSEL
System PLL Selected
0 System PLL is not the system clock source
1 System PLL is the system clock source
Table continues on the next page...
Memory Map/Register Definition
Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019
476 NXP Semiconductors