NXP Semiconductors KE1xF Series, Reference Manual, Page: 477 / 1483

SCG_SPLLCSR field descriptions (continued)
Field Description
24
SPLLVLD
System PLL Valid
Indicates when the SPLL clock is valid. When the System PLL (SPLL) is disabled, the System PLL Valid
bit (SPLLVLD) will clear without causing the System PLL Clock Error bit (SPLLERR) to get set. In a similar
way, if the System PLL (SPLL) is using the System Oscillator (SOSC) as its reference clock, and a System
OSC Clock Error (SOSCCSR[SOSCERR]) is detected, then the System PLL Valid bit (SPLLVLD) will clear
without asserting a System PLL Clock Error (SPLLERR).
Lock detect is determined by a lock detect circuit. Three samples of lock detect determines whether or not
the clock is valid.
NOTE: The System PLL Valid bit (SPLLVLD) should only be used to verify that the SPLL is locked after
initialization. To monitor the SPLL clock, ensure that the System PLL Clock Monitor is enabled,
using the System PLL Clock Monitor bit (SPLLCM).
0 System PLL is not enabled or clock is not valid
1 System PLL is enabled and output clock is valid
23
LK
Lock Register
This bit field can be cleared/set at any time.
0 Control Status Register can be written.
1 Control Status Register cannot be written.
22–18
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
17
SPLLCMRE
System PLL Clock Monitor Reset Enable
0 Clock Monitor generates interrupt when error detected
1 Clock Monitor generates reset when error detected
16
SPLLCM
System PLL Clock Monitor
Enables the clock monitor, if the clock source is disabled in a low power mode then the clock monitor is
also disabled in the low power mode. When the clock monitor is disabled in a low power mode, it remains
disabled until the clock valid flag is set following exit from the low power mode.
0 System PLL Clock Monitor is disabled
1 System PLL Clock Monitor is enabled
15–2
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
1
SPLLSTEN
System PLL Stop Enable
0 System PLL is disabled in Stop modes
1 System PLL is enabled in Stop modes
0
SPLLEN
System PLL Enable
NOTE: If this bit written during clock switching, it should be read back and confirmed before proceeding.
As the device exits reset, the SCG_RCCR register should be configured as per the supported
frequency ranges of the device BEFORE enabling the SPLL (SPLLEN =1).
0 System PLL is disabled
1 System PLL is enabled
Chapter 19 System Clock Generator (SCG)
Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019
NXP Semiconductors 477