NXP Semiconductors KE1xF Series, Reference Manual, Page: 478 / 1483

19.3.20 System PLL Divide Register (SCG_SPLLDIV)
Changes to SPLLDIV should be done when System PLL is disabled to prevent glitches to
output divided clock.
Address: 4006_4000h base + 604h offset = 4006_4604h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
SPLLDIV2
0
SPLLDIV1
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SCG_SPLLDIV field descriptions
Field Description
31–19
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
18–16
Reserved
This field is reserved.
This bit field is reserved. Software should write 0 to this bit field to maintain compatibility.
15–11
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
10–8
SPLLDIV2
System PLL Clock Divide 2
Clock divider 2 for System PLL. Used by modules that need an asynchronous clock source.
000 Clock disabled
001 Divide by 1
010 Divide by 2
011 Divide by 4
100 Divide by 8
101 Divide by 16
110 Divide by 32
111 Divide by 64
7–3
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
SPLLDIV1 System PLL Clock Divide 1
Clock divider 1 for System PLL. Used to generate the clock source for modules that need an
asynchronous clock source.
000 Clock disabled
001 Divide by 1
010 Divide by 2
011 Divide by 4
100 Divide by 8
Table continues on the next page...
Memory Map/Register Definition
Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019
478 NXP Semiconductors