NXP Semiconductors KE1xF Series, Reference Manual, Page: 457 / 1483

19.3.5 VLPR Clock Control Register (SCG_VCCR)
This register controls the system clock source and the system clock dividers for the core,
platform, external and bus clock domains when in VLPR mode only. This register can
only be written using a 32-bit write. Selecting a different clock source when in VLPR
requires that clock source to be enabled first and be valid before system clocks switch to
that clock source. If system clock divide ratios also change when selecting a different
clock mode when in VLPR, new system clock divide ratios will not take affect until new
clock source is valid.
Address: 4006_4000h base + 18h offset = 4006_4018h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
SCS
0
DIVCORE Reserved
0
DIVBUS DIVSLOW
W
Reset
0 0 0 0 0 0 1 0 0 0 0 0 * * * * 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
* Notes:
DIVCORE field: The reset value is controlled by user FOPT bits that get uploaded during reset. The two option reset values
are div-by-4 and div-by-8.
•
SCG_VCCR field descriptions
Field Description
31–28
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
27–24
SCS
System Clock Source
Selects the clock source generating the system clock in VLPR mode. Attempting to select a clock that is
not valid will be ignored. Selects the clock source generating the system clock. Selecting a different clock
source when in VLPR mode requires that clock source to be enabled first and be valid before system
clocks switch to that clock source.
0000 Reserved
0001 System OSC (SOSC_CLK)
0010 Slow IRC (SIRC_CLK)
0011 Reserved
0100 Reserved
0101 Reserved
0110 Reserved
0111 Reserved
23–20
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
19–16
DIVCORE
Core Clock Divide Ratio
0000 Divide-by-1
0001 Divide-by-2
0010 Divide-by-3
Table continues on the next page...
Chapter 19 System Clock Generator (SCG)
Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019
NXP Semiconductors 457