18
Keysight EXG and MXG X-Series Signal Generators User’s Guide
Signal Generator Overview
Rear Panel Overview (N5171B, N5172B, N5181B, & N5182B)
Markers (pins 1-4)
Each Arb–based waveform point has a marker on/off condition associated with it.
Each real-time signal can be routed to the output marker signals using SCPI commands or the real-time personalities.
Marker level = +3.3 V high (positive polarity selected); 0V low (negative polarity selected).
Event 1 (pin 1)
Pin 1 outputs a pulse that can be used to trigger the start of a data pattern, frame, or timeslot.
Adjustable to ± one timeslot; resolution = one bit
Data Clock Out (pin 7)
Pin 7 is used with an internal baseband generator. This pin relays a CMOS bit clock signal for synchronizing serial data.
Data In (pin 23)
Pin 23 accepts an externally supplied CMOS-compatible signal data input used with digital modulation applications. The
expected input is a CMOS signal where a CMOS high is equivalent to a data 1 and a CMOS low is equivalent to a data 0.
The maximum input data rate is 50 Mb/s. The data must be valid on the DATA CLOCK
falling edges.
Symbol Sync In (pin 25)
Pin 25 accepts an externally supplied symbol sync signal for use with digital modulation applications.
Data Clock In (pin 29)
Pin 29 accepts an externally supplied CMOS-compatible signal data-clock input used with digital modulation applications.
The expected input is a MCOS bit clock signal where the rising edge is aligned with the beginning data bit. The falling edge
is used to clock the DATA and SYMBOL SYNC signals.
The maximum clock rate is 50 MHz.
Event 2 (pin 31)
Pin 31 outputs data enable signal for gating external equipment. The output is applicable when the external data is clocked
into internally generated timeslots. Data is enabled when the signal is low.
