Keysight EXG and MXG X-Series Signal Generators User’s Guide
291
Digital Signal Interface Module (Option 003/004)
Clock Timing
Clock Timing for Parallel Data
Some components require multiple clocks during a single sample period. (A sample period consists
of an I and Q sample). For parallel data transmissions, you can select one, two, or four clocks per
sample. For clocks per sample greater than one, the I and Q samples are held constant to
accommodate the additional clock periods. This reduces the sample rate relative to the clock rate
by a factor equal to the clocks per sample selection. For example, when four is selected, the sample
rate is reduced by a factor of four (sample rate to clock rate ratio).
demonstrates the
clock timing for each clocks per sample selection. For input mode, the clocks per sample setting is
always one.
Figure 10-4
Clock Sample Timing for Parallel Port Configuration
1 Sample Period
Q sample
1 Clock Per Sample
1 Clock
Clock and sample rates are the same
I sample
Clock
4 bits per word
4 bits per word
