Keysight EXG and MXG X-Series Signal Generators User’s Guide
313
Digital Signal Interface Module (Option 003/004)
Operating the N5102A Module in Input Mode
clock rate under the clock setup menu.
804
Digital module input FIFO underflow error; There are not
enough samples being produced for the current clock rate.
Verify that the digital module clock is set up properly.
This error is reported when the digital module clock setup is not
synchronized with the rate the samples are entering the digital
module. Verify that the input clock rate matches the specified
clock rate under the clock setup menu.
Figure 10-20
Clock Setup Softkey Menu for a Parallel Port Configuration
The top graphic on the display shows the current clock source that provides the output clock
signal at the Clock Out and Device Interface connectors. The graphic changes to reflect the
clock source selection discussed later in this procedure. The bottom graphic shows the clock
edges relative to the data. The displayed clock signal will change to reflect the following:
—
clock phase choice
—
clock skew adjustment
—
clock polarity selection
2.
Press the
Clock Source
softkey.
Inactive for Input mode
Active for only the Internal clock source selection
Inactive for clock rates below 25 MHz
Inactive for clock rates below
10 MHz and above 200 MHz
