Intel 80C186EA, User Manual

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3-35
BUS INTERFACE UNIT
Figure 3-30. Exiting HALT (Active/Idle Mode)
3.6 SYSTEM DESIGN ALTERNATIVES
Most system designs require no signals other than those already provided by the BIU. However,
heavily loaded bus conditions, slow memory or peripheral device performance and off-board de-
vice interfaces may not be supported directly without modifying the BIU interface. The following
sections deal with topics to enhance or modify the operation of the BIU.
CLKOUT
AD15:0
[AD7:0]
ALE
[A15:8]
A19:16
Note 3
NOTES:
1. For NMI, delay = 4 1/2 clocks. For INTx, delay = 7 1/2 clocks (min).
2. If previous bus cycle was a read, bus will float. If previous bus cycle was
a write, bus will drive data value.
3. Previous bus cycle value.
4. If previous bus cycle was a refresh or DMA bus cycle, value will be
8H (A19 = 1); otherwise, value will be 0.
S2:0
BHE
RFSH
Note 4
NMI/INTx
Address
Note 3
Addr Note 2
Note 1
Valid
A1055-0A