Intel 80C186EA, User Manual

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8-5
INTERRUPT CONTROL UNIT
8.3 FUNCTIONAL OPERATION IN MASTER MODE
This section covers the process in which the Interrupt Control Unit receives interrupts and asserts
the maskable interrupt request to the CPU.
8.3.1 Typical Interrupt Sequence
When the Interrupt Control Unit first detects an interrupt, it sets the corresponding bit in the In-
terrupt Request register to indicate that the interrupt is pending. The Interrupt Control Unit checks
all pending interrupt sources. If the interrupt is unmasked and meets the priority criteria (see “Pri-
ority Resolution” on page 8-5), the Interrupt Control Unit asserts the maskable interrupt request
to the CPU, then waits for the interrupt acknowledge.
When the Interrupt Control Unit receives the interrupt acknowledge, it passes the interrupt type
to the CPU. At that point, the CPU begin the interrupt processing sequence.(See “Interrupt/Ex-
ception Processing” on page 2-39 for details.) The Interrupt Control Unit always passes the vector
that has the highest priority at the time the acknowledge is received. If a higher priority interrupt
occurs before the interrupt acknowledge, the higher priority interrupt has precedence.
When it receives the interrupt acknowledge, the Interrupt Control Unit clears the corresponding
bit in the Interrupt Request register and sets the corresponding bit in the In-Service register. The
In-Service register keeps track of which interrupt handlers are being processed. At the end of an
interrupt handler, the programmer must issue an End-of-Interrupt (EOI) command to explicitly
clear the In-Service register bit. If the bit remains set, the Interrupt Control Unit cannot process
any additional interrupts from that source.
8.3.2 Priority Resolution
The decision to assert the maskable interrupt request to the CPU is somewhat complicated. The
complexity is needed to support interrupt nesting. First, an interrupt occurs and the corre-
sponding Interrupt Request register bit is set. The Interrupt Control Unit then asserts the
maskable interrupt request to the CPU, if the pending interrupt satisfies these requirements:
1. its Interrupt Mask bit is cleared (it is unmasked)
2. its priority is higher than the value in the Priority Mask register
3. its In-Service bit is cleared
4. its priority is equal to or greater than that of any interrupt whose In-Service bit is set
The In-Service register keeps track of interrupt handler execution. The Interrupt Control Unit
uses this information to decide whether another interrupt source has sufficient priority to preempt
an interrupt handler that is executing.