Intel 80C186EA, User Manual

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DIRECT MEMORY ACCESS UNIT
10-8
10.1.8 DMA Unit Interrupts
Each DMA channel can be programmed to generate an interrupt request when its transfer count
reaches zero.
10.1.9 DMA Cycles and the BIU
The DMA Unit uses the Bus Interface Unit to perform its transfers. When the DMA Unit has a
pending request, it signals the BIU. If the BIU has no other higher-priority request pending, it runs
the DMA cycle. (BIU priority is described in Chapter 3, “Bus Interface Unit.”) The BIU signals
that it is running a bus cycle initiated by a master other than the CPU by driving the S6 status bit
high.
The Chip-Select Unit monitors the BIU addresses to determine which chip-select, if any, to acti-
vate. Because the DMA Unit uses the BIU, chip-selects are active for DMA cycles. If a DMA
channel accesses a region of memory or I/O space within a chip-select’s programmed range, then
that chip-select is asserted during the cycle. The Chip-Select Unit will not recognize DMA cycles
that access I/O space above 64K.
10.1.10 The Two-Channel DMA Unit
Two DMA channels are combined with arbitration logic to form the DMA Unit (see Figure 10-5).
10.1.10.1 DMA Channel Arbitration
Within the two-channel DMA Unit, the arbitration logic decides which channel takes precedence
when both channels simultaneously request transfers. Each channel can be set to either low pri-
ority or high priority. If the two channels are set to the same priority (either both high or both
low), then the channels rotate priority.
10.1.10.1.1 Fixed Priority
Fixed priority results when one channel in a module is programmed to high priority and the other
is set to low priority. If both DMA requests occur simultaneously, the high priority channel per-
forms its transfer (or transfers) first. The high priority channel continues to perform transfers as
long as the following conditions are met:
•
the channel’s DMA request is still active
•
the channel has not terminated or suspended transfers (through programming or interrupts)
•
the channel has not released the bus (through the insertion of idle states for destination-
synchronized transfers)