CLOCK GENERATION AND POWER MANAGEMENT
5-2
5.1.1.1 Oscillator Operation
A phase shift oscillator operates through positive feedback, where a non-inverted, amplified ver-
sion of the input connects back to the input. A 360° phase shift around the loop will sustain the
feedback in the oscillator. The on-chip inverter provides a 180° phase shift. The combination of
the inverter’s output impedance and the first load capacitor (see Figure 5-2) provides another 90°
phase shift. At resonance, the crystal becomes primarily resistive. The combination of the crystal
and the second load capacitor provides the final 90° phase shift. Above and below resonance, the
crystal is reactive and forces the oscillator back toward the crystal’s nominal frequency.
Figure 5-2. Ideal Operation of Pierce Oscillator
Figure 5-3 shows the actual microprocessor crystal connections. For low frequencies, crystal ven-
dors offer fundamental mode crystals. At higher frequencies, a third overtone crystal is the only
choice. The external capacitors, C
X1
at CLKIN and C
X2
at OSCOUT, together with stray capaci-
tance, form the load. A third overtone crystal requires an additional inductor L
1
and capacitor C
1
to select the third overtone frequency and reject the fundamental frequency. See “Selecting Crys-
tals” on page 5-5 for a more detailed discussion of crystal vibration modes.
90˚
180˚
90˚
NOTE:
At resonance, the crystal is essentially resistive.
Above resonance, the crystal is inductive.
Below resonance, the crystal is capacitive.
Z = Inverter Output Z
0
A1125-0A
Summary of Contents for 80C186EA
Page 1: ...80C186EA 80C188EA Microprocessor User s Manual...
Page 2: ...80C186EA 80C188EA Microprocessor User s Manual 1995...
Page 19: ......
Page 20: ...1 Introduction...
Page 21: ......
Page 28: ...2 Overview of the 80C186 Family Architecture...
Page 29: ......
Page 79: ......
Page 80: ...3 Bus Interface Unit...
Page 81: ......
Page 129: ......
Page 130: ...4 Peripheral Control Block...
Page 131: ......
Page 139: ......
Page 140: ...5 ClockGenerationand Power Management...
Page 141: ......
Page 165: ......
Page 166: ...6 Chip Select Unit...
Page 167: ......
Page 190: ...7 Refresh Control Unit...
Page 191: ......
Page 205: ......
Page 206: ...8 Interrupt Control Unit...
Page 207: ......
Page 239: ...INTERRUPT CONTROL UNIT 8 32...
Page 240: ...9 Timer Counter Unit...
Page 241: ......
Page 265: ......
Page 266: ...10 Direct Memory Access Unit...
Page 267: ......
Page 295: ...DIRECT MEMORY ACCESS UNIT 10 28...
Page 296: ...11 Math Coprocessing...
Page 297: ......
Page 314: ...12 ONCE Mode...
Page 315: ......
Page 318: ...A 80C186 Instruction Set Additions and Extensions...
Page 319: ......
Page 330: ...B Input Synchronization...
Page 331: ......
Page 334: ...C Instruction Set Descriptions...
Page 335: ......
Page 383: ...INSTRUCTION SET DESCRIPTIONS C 48...
Page 384: ...D Instruction Set Opcodes and Clock Cycles...
Page 385: ......
Page 408: ...Index...
Page 409: ......