Intel 80C186EA, User Manual

Page: 284 / 417

10-17
DIRECT MEMORY ACCESS UNIT
Figure 10-11. DMA Control Register (Continued)
10.2.1.3 Selecting the Source of DMA Requests
DMA requests can come from either an internal source (Timer 2) or an external source.
Internal DMA requests are selected by setting the IDRQ bit in the DMA Control Register (see
Figure 10-11 on page 10-15) for the channel. The DMA channel ignores its DRQ pin when inter-
nal requests are programmed. Similarly, the DMA channel responds only to the DRQ pin (and
ignores internal requests) when external requests are selected.
Register Name: DMA Control Register
Register Mnemonic: DxCON
Register Function: Controls DMA channel parameters.
Bit
Mnemonic
Bit Name
Reset
State
Function
CHG Change
Start Bit X Set CHG to enable modifying the STRT bit.
STRT Start DMA
Channel 0 Set STRT to arm the DMA channel. The STRT bit can
be modified only when the CHG bit is set.
WORD Word
Transfer
Select X Set WORD to select word transfers; clear WORD to
select byte transfers. The 8-bit bus versions of the
device ignore the WORD bit.
NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a
logic zero to ensure compatibility with future Intel products.
15 0
S
T
R
T
C
H
G
W
O
R
D
P S
Y
N
0
S
Y
N
1
I
D
R
Q
T
C
S
I
N
C
S
D
E
C I
N
T
D
I
N
C
D
D
E
C D
M
E
M
S
M
E
M
A1180-0A