8-1
CHAPTER 8
INTERRUPT CONTROL UNIT
The 80C186 Modular Core has a single maskable interrupt input. (See “Interrupts and Exception
Handling” on page 2-39.) The Interrupt Control Unit (ICU) expands the interrupt capabilities be-
yond a single input. To fulfill this function, the Interrupt Control Unit operates in either of two
modes: Master or Slave.
In Master mode, the ICU controls the maskable interrupt input to the CPU. Interrupts can origi-
nate from the on-chip peripherals and from four external interrupt pins. The ICU synchronizes
and prioritizes all interrupt sources and presents the correct interrupt type vector to the CPU. (See
Figure 8-1.) Most systems use master mode.
In Slave mode, an external 8259A module controls the maskable interrupt input to the CPU and
acts as the master interrupt controller. The ICU processes only those interrupts from the on-chip
peripherals and acts as an interrupt input to the 8259A. (See Figure 8-15 on page 8-24.) This mode
can be useful in larger system designs.
The Interrupt Control Unit has the following features:
•
Programmable priority of each interrupt source
•
Individual masking of each interrupt source
•
Nesting of interrupt sources
•
Support for polled operation
•
Support for cascading external 8259A modules to expand external interrupt sources
8.1 FUNCTIONAL OVERVIEW
All microcomputer systems must communicate in some way with the external world. A typical
system might have a keyboard, a disk drive and a communications port, all requiring CPU atten-
tion at different times. There are two distinct ways to process peripheral I/O requests: polling and
interrupts.
Polling requires that the CPU check each peripheral device in the system periodically to see
whether it requires servicing. It would not be unusual to poll a low-speed peripheral (a serial port,
for instance) thousands of times before it required servicing. In most cases, the use of polling has
a detrimental effect on system throughput. Any time used to check the peripherals is time spent
away from the main processing tasks.
Summary of Contents for 80C186EA
Page 1: ...80C186EA 80C188EA Microprocessor User s Manual...
Page 2: ...80C186EA 80C188EA Microprocessor User s Manual 1995...
Page 19: ......
Page 20: ...1 Introduction...
Page 21: ......
Page 28: ...2 Overview of the 80C186 Family Architecture...
Page 29: ......
Page 79: ......
Page 80: ...3 Bus Interface Unit...
Page 81: ......
Page 129: ......
Page 130: ...4 Peripheral Control Block...
Page 131: ......
Page 139: ......
Page 140: ...5 ClockGenerationand Power Management...
Page 141: ......
Page 165: ......
Page 166: ...6 Chip Select Unit...
Page 167: ......
Page 190: ...7 Refresh Control Unit...
Page 191: ......
Page 205: ......
Page 206: ...8 Interrupt Control Unit...
Page 207: ......
Page 239: ...INTERRUPT CONTROL UNIT 8 32...
Page 240: ...9 Timer Counter Unit...
Page 241: ......
Page 265: ......
Page 266: ...10 Direct Memory Access Unit...
Page 267: ......
Page 295: ...DIRECT MEMORY ACCESS UNIT 10 28...
Page 296: ...11 Math Coprocessing...
Page 297: ......
Page 314: ...12 ONCE Mode...
Page 315: ......
Page 318: ...A 80C186 Instruction Set Additions and Extensions...
Page 319: ......
Page 330: ...B Input Synchronization...
Page 331: ......
Page 334: ...C Instruction Set Descriptions...
Page 335: ......
Page 383: ...INSTRUCTION SET DESCRIPTIONS C 48...
Page 384: ...D Instruction Set Opcodes and Clock Cycles...
Page 385: ......
Page 408: ...Index...
Page 409: ......