INSTRUCTION SET OPCODES AND CLOCK CYCLES
D-4
ARITHMETIC INSTRUCTIONS (Continued)
SUB = Subtract
reg/memory with register to either
0 0 1 0 1 0 d w
mod reg r/m
3/10
immediate from register/memory
1 0 0 0 0 0 s w
mod 101 r/m
data
data if sw=01
4/16
immediate from accumulator
0 0 0 1 1 1 0 w
data
data if w=1
3/4
(1)
SBB = Subtract with borrow
reg/memory with register to either
0 0 0 1 1 0 d w
mod reg r/m
3/10
immediate from register/memory
1 0 0 0 0 0 s w
mod 011 r/m
data
data if sw=01
4/16
immediate from accumulator
0 0 0 1 1 1 0 w
data
data if w=1
3/4
(1)
DEC = Decrement
register/memory
1 1 1 1 1 1 1 w
mod 001 r/m
3/15
register
0 1 0 0 1 reg
3
NEG = Change sign
1 1 1 1 0 1 1 w
mod reg r/m
3
CMP = Compare
register/memory with register
0 0 1 1 1 0 1 w
mod reg r/m
3/10
register with register/memory
0 0 1 1 1 0 0 w
mod reg r/m
3/10
immediate with register/memory
1 0 0 0 0 0 s w
mod 111 r/m
data
data if sw=01
3/10
immediate with accumulator
0 0 1 1 1 1 0 w
data
data if w=1
3/4
(1)
AAS = ASCII adjust for subtraction
0 0 1 1 1 1 1 1
7
DAS = Decimal adjust for subtraction
0 0 1 0 1 1 1 1
4
MUL = multiply (unsigned)
1 1 1 1 0 1 1 w
mod 100 r/m
register-byte
26-28
register-word
35-37
memory-byte
32-34
memory-word
41-43
IMUL = Integer multiply (signed)
1 1 1 1 0 1 1 w
mod 101 r/m
register-byte
25-28
register-word
34-37
memory-byte
31-34
memory-word
40-43
integer immediate multiply (signed)
0 1 1 0 1 0 s 1
mod reg r/m
data
data if s=0
22-25/
29-32
Table D-2. Instruction Set Summary (Continued)
Function
Format
Clocks
Notes
NOTES:
1. Clock cycles are given for 8-bit/16-bit operations.
2. Clock cycles are given for jump not taken/jump taken.
3. Clock cycles are given for interrupt taken/interrupt not taken.
4. If TEST = 0
Shading indicates additions and enhancements to the 8086/8088 instruction set. See Appendix A, “80C186
Instruction Set Additions and Extensions,” for details.
Summary of Contents for 80C186EA
Page 1: ...80C186EA 80C188EA Microprocessor User s Manual...
Page 2: ...80C186EA 80C188EA Microprocessor User s Manual 1995...
Page 19: ......
Page 20: ...1 Introduction...
Page 21: ......
Page 28: ...2 Overview of the 80C186 Family Architecture...
Page 29: ......
Page 79: ......
Page 80: ...3 Bus Interface Unit...
Page 81: ......
Page 129: ......
Page 130: ...4 Peripheral Control Block...
Page 131: ......
Page 139: ......
Page 140: ...5 ClockGenerationand Power Management...
Page 141: ......
Page 165: ......
Page 166: ...6 Chip Select Unit...
Page 167: ......
Page 190: ...7 Refresh Control Unit...
Page 191: ......
Page 205: ......
Page 206: ...8 Interrupt Control Unit...
Page 207: ......
Page 239: ...INTERRUPT CONTROL UNIT 8 32...
Page 240: ...9 Timer Counter Unit...
Page 241: ......
Page 265: ......
Page 266: ...10 Direct Memory Access Unit...
Page 267: ......
Page 295: ...DIRECT MEMORY ACCESS UNIT 10 28...
Page 296: ...11 Math Coprocessing...
Page 297: ......
Page 314: ...12 ONCE Mode...
Page 315: ......
Page 318: ...A 80C186 Instruction Set Additions and Extensions...
Page 319: ......
Page 330: ...B Input Synchronization...
Page 331: ......
Page 334: ...C Instruction Set Descriptions...
Page 335: ......
Page 383: ...INSTRUCTION SET DESCRIPTIONS C 48...
Page 384: ...D Instruction Set Opcodes and Clock Cycles...
Page 385: ......
Page 408: ...Index...
Page 409: ......