Intel 80C186EA, User Manual

Page: 216 / 417

8-9
INTERRUPT CONTROL UNIT
8.3.4 Interrupt Acknowledge Sequence
During the interrupt acknowledge sequence, the Interrupt Control Unit passes the interrupt type
to the CPU. The CPU then multiplies the interrupt type by four to derive the interrupt vector ad-
dress in the interrupt vector table. (“Interrupt/Exception Processing” on page 2-39 describes the
interrupt acknowledge sequence and Figure 2-25 on page 2-40 illustrates the interrupt vector ta-
ble.)
The interrupt types for all sources are fixed and unalterable (see Table 8-2). The Interrupt Control
Unit passes these types to the CPU internally. The first external indication of the interrupt ac-
knowledge sequence is the CPU fetch from the interrupt vector table.
In cascade mode, the external 8259A supplies the interrupt type. In this case, the CPU runs an
external interrupt acknowledge cycle to fetch the interrupt type from the 8259A (see “Interrupt
Acknowledge Bus Cycle” on page 3-25).
8.3.5 Polling
In some applications, it is desirable to poll the Interrupt Control Unit. The CPU polls the Interrupt
Control Unit for any pending interrupts, and software can service interrupts whenever it is con-
venient. The Poll and Poll Status registers support polling.
Software reads the Poll register to get the type of the highest priority pending interrupt, then calls
the corresponding interrupt handler. Reading the Poll register also acknowledges the interrupt.
This clears the Interrupt Request bit and sets the In-Service bit for the interrupt. The Poll Status
register has the same format as the Poll register, but reading the Poll Status register does not ac-
knowledge the interrupt.
Table 8-2. Fixed Interrupt Types
Interrupt Name Interrupt Type
Timer 0 8
Timer 1 18
Timer 2 19
DMA0 10
DMA1 11
INT0 12
INT1 13
INT2 14
INT3 15