Intel 80C186EA, User Manual

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OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
2.1.10 Stack Implementation
Stacks in the 80C186 Modular Core family reside in memory space. They are located by the Stack
Segment register (SS) and the Stack Pointer (SP). A system can have multiple stacks, but only
one stack is directly addressable at a time. A stack can be up to 64 Kbytes long, the maximum
length of a segment. Growing a stack segment beyond 64 Kbytes overwrites the beginning of the
segment. The SS register contains the base address of the current stack. The top of the stack, not
the base address, is the origination point of the stack. The SP register contains an offset that points
to the Top of Stack (TOS).
Stacks are 16 bits wide. Instructions operating on a stack add and remove stack elements one
word at a time. An element is pushed onto the stack (see Figure 2-10) by first decrementing the
SP register by 2 and then writing the data word. An element is popped off the stack by copying
it from the top of the stack and then incrementing the SP register by 2. The stack grows down in
memory toward its base address. Stack operations never move or erase elements on the stack. The
top of the stack changes only as a result of updating the stack pointer.
2.1.11 Reserved Memory and I/O Space
Two specific areas in memory and one area in I/O space are reserved in the 80C186 Core family.
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Locations 0H through 3FFH in low memory are used for the Interrupt Vector Table.
Programs should not be loaded here.
•
Locations 0FFFF0H through 0FFFFFH in high memory are used for system reset code
because the processor begins execution at 0FFFF0H.
•
Locations 0F8H through 0FFH in I/O space are reserved for communication with other Intel
hardware products and must not be used. On the 80C186 core, these addresses are used as
I/O ports for the 80C187 numerics processor extension.