C-7
INSTRUCTION SET DESCRIPTIONS
BOUND
Detect Value Out of Range:
BOUND
dest, src
Provides array bounds checking in
hardware. The calculated array index
is placed in one of the general purpose
registers, and the upper and lower
bounds of the array are placed in two
consecutive memory locations. The
contents of the register are compared
with the memory location values, and if
the register value is less than the first
location or greater than the second
memory location, a trap type 5 is
generated.
Instruction Operands:
BOUND reg, mem
if
((dest) < (src) or (dest) > ((src) + 2)
then
(SP)
←
(SP) – 2
((SP) + 1 : (SP))
←
FLAGS
(IF)
←
0
(TF)
←
0
(SP)
←
(SP) – 2
((SP) + 1 : (SP))
←
(CS)
(CS)
←
(1EH)
(SP)
←
(SP) – 2
((SP) + 1 : (SP))
←
(IP)
(IP)
←
(1CH)
AF –
CF –
DF –
IF –
OF –
PF –
SF –
TF –
ZF –
CALL
Call Procedure:
CALL procedure-name
Activates an out-of-line procedure,
saving information on the stack to
permit a RET (return) instruction in the
procedure to transfer control back to
the instruction following the CALL. The
assembler generates a different type
of CALL instruction depending on
whether the programmer has defined
the procedure name as NEAR or FAR.
Instruction Operands:
CALL near-proc
CALL far-proc
CALL memptr16
CALL regptr16
CALL memptr32
if
Inter-segment
then
(SP)
←
(SP) – 2
((SP) +1:(SP))
←
(CS)
(CS)
←
SEG
(SP)
←
(SP) – 2
((SP) +1:(SP))
←
(IP)
(IP)
←
dest
AF –
CF –
DF –
IF –
OF –
PF –
SF –
TF –
ZF –
Table C-4. Instruction Set (Continued)
Name
Description
Operation
Flags
Affected
NOTE: The three symbols used in the Flags Affected column are defined as follows:
– the contents of the flag remain unchanged after the instruction is executed
? the contents of the flag is undefined after the instruction is executed
ü
the flag is updated after the instruction is executed
Summary of Contents for 80C186EA
Page 1: ...80C186EA 80C188EA Microprocessor User s Manual...
Page 2: ...80C186EA 80C188EA Microprocessor User s Manual 1995...
Page 19: ......
Page 20: ...1 Introduction...
Page 21: ......
Page 28: ...2 Overview of the 80C186 Family Architecture...
Page 29: ......
Page 79: ......
Page 80: ...3 Bus Interface Unit...
Page 81: ......
Page 129: ......
Page 130: ...4 Peripheral Control Block...
Page 131: ......
Page 139: ......
Page 140: ...5 ClockGenerationand Power Management...
Page 141: ......
Page 165: ......
Page 166: ...6 Chip Select Unit...
Page 167: ......
Page 190: ...7 Refresh Control Unit...
Page 191: ......
Page 205: ......
Page 206: ...8 Interrupt Control Unit...
Page 207: ......
Page 239: ...INTERRUPT CONTROL UNIT 8 32...
Page 240: ...9 Timer Counter Unit...
Page 241: ......
Page 265: ......
Page 266: ...10 Direct Memory Access Unit...
Page 267: ......
Page 295: ...DIRECT MEMORY ACCESS UNIT 10 28...
Page 296: ...11 Math Coprocessing...
Page 297: ......
Page 314: ...12 ONCE Mode...
Page 315: ......
Page 318: ...A 80C186 Instruction Set Additions and Extensions...
Page 319: ......
Page 330: ...B Input Synchronization...
Page 331: ......
Page 334: ...C Instruction Set Descriptions...
Page 335: ......
Page 383: ...INSTRUCTION SET DESCRIPTIONS C 48...
Page 384: ...D Instruction Set Opcodes and Clock Cycles...
Page 385: ......
Page 408: ...Index...
Page 409: ......