OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
2-34
Based index addressing generates an effective address that is the sum of a base register, an index
register and a displacement (see Figure 2-19). The two address components can be determined at
execution time, making this a very flexible addressing mode.
Figure 2-19. Based Index Addressing
Based index addressing provides a convenient way for a procedure to address an array located on
a stack (see Figure 2-20). The BP register can contain the offset of a reference point on the stack.
This is typically the top of the stack after the procedure has saved registers and allocated local
storage. The offset of the beginning of the array from the reference point can be expressed by a
displacement value. The index register can be used to access individual array elements. Arrays
contained in structures and matrices (two-dimensional arrays) can also be accessed with based
indexed addressing.
String instructions do not use normal memory addressing modes to access operands. Instead, the
index registers are used implicitly (see Figure 2-21). When a string instruction executes, the SI
register must point to the first byte or word of the source string, and the DI register must point to
the first byte or word of the destination string. In a repeated string operation, the CPU will auto-
matically adjust the SI and DI registers to obtain subsequent bytes or words. For string instruc-
tions, the DS register is the default segment register for the SI register and the ES register is the
default segment register for the DI register. This allows string instructions to operate on data lo-
cated anywhere within the 1 Mbyte address space.
EA
BP
BX
SI
DI
Opcode
Mod R/M
Displacement
or
or
+
+
A1022-0A
Summary of Contents for 80C186EA
Page 1: ...80C186EA 80C188EA Microprocessor User s Manual...
Page 2: ...80C186EA 80C188EA Microprocessor User s Manual 1995...
Page 19: ......
Page 20: ...1 Introduction...
Page 21: ......
Page 28: ...2 Overview of the 80C186 Family Architecture...
Page 29: ......
Page 79: ......
Page 80: ...3 Bus Interface Unit...
Page 81: ......
Page 129: ......
Page 130: ...4 Peripheral Control Block...
Page 131: ......
Page 139: ......
Page 140: ...5 ClockGenerationand Power Management...
Page 141: ......
Page 165: ......
Page 166: ...6 Chip Select Unit...
Page 167: ......
Page 190: ...7 Refresh Control Unit...
Page 191: ......
Page 205: ......
Page 206: ...8 Interrupt Control Unit...
Page 207: ......
Page 239: ...INTERRUPT CONTROL UNIT 8 32...
Page 240: ...9 Timer Counter Unit...
Page 241: ......
Page 265: ......
Page 266: ...10 Direct Memory Access Unit...
Page 267: ......
Page 295: ...DIRECT MEMORY ACCESS UNIT 10 28...
Page 296: ...11 Math Coprocessing...
Page 297: ......
Page 314: ...12 ONCE Mode...
Page 315: ......
Page 318: ...A 80C186 Instruction Set Additions and Extensions...
Page 319: ......
Page 330: ...B Input Synchronization...
Page 331: ......
Page 334: ...C Instruction Set Descriptions...
Page 335: ......
Page 383: ...INSTRUCTION SET DESCRIPTIONS C 48...
Page 384: ...D Instruction Set Opcodes and Clock Cycles...
Page 385: ......
Page 408: ...Index...
Page 409: ......