11-1
CHAPTER 11
MATH COPROCESSING
The 80C186 Modular Core Family meets the need for a general-purpose embedded microproces-
sor. In most data control applications, efficient data movement and control instructions are fore-
most and arithmetic performed on the data is simple. However, some applications do require
more powerful arithmetic instructions and more complex data types than those provided by the
80C186 Modular Core.
11.1 OVERVIEW OF MATH COPROCESSING
Applications needing advanced mathematics capabilities have the following characteristics.
•
Numeric data values are non-integral or vary over a wide range
•
Algorithms produce very large or very small intermediate results
•
Computations must be precise (i.e., calculations must retain several significant digits)
•
Computations must be reliable without dependence on programmed algorithms
•
Overall math performance exceeds that afforded by a general-purpose processor and
software alone
For the 80C186 Modular Core family, the 80C187 math coprocessor satisfies the need for pow-
erful mathematics. The 80C187 can increase the math performance of the microprocessor system
by 50 to 100 times.
11.2 AVAILABILITY OF MATH COPROCESSING
The 80C186 Modular Core supports the 80C187 with a hardware interface under microcode con-
trol. However, not all proliferations support the 80C187. Some package types have insufficient
leads to support the required external handshaking requirements. The 3-volt versions of the pro-
cessor do not specify math coprocessing because the 80C187 has only a 5-volt rating. Please refer
to the current data sheets for details.
To execute numerics instructions, the 80C186EA must exit reset in Numerics Mode. The proces-
sor checks its TEST pin at reset and automatically enters Numerics Mode if the math coprocessor
is present.
Summary of Contents for 80C186EA
Page 1: ...80C186EA 80C188EA Microprocessor User s Manual...
Page 2: ...80C186EA 80C188EA Microprocessor User s Manual 1995...
Page 19: ......
Page 20: ...1 Introduction...
Page 21: ......
Page 28: ...2 Overview of the 80C186 Family Architecture...
Page 29: ......
Page 79: ......
Page 80: ...3 Bus Interface Unit...
Page 81: ......
Page 129: ......
Page 130: ...4 Peripheral Control Block...
Page 131: ......
Page 139: ......
Page 140: ...5 ClockGenerationand Power Management...
Page 141: ......
Page 165: ......
Page 166: ...6 Chip Select Unit...
Page 167: ......
Page 190: ...7 Refresh Control Unit...
Page 191: ......
Page 205: ......
Page 206: ...8 Interrupt Control Unit...
Page 207: ......
Page 239: ...INTERRUPT CONTROL UNIT 8 32...
Page 240: ...9 Timer Counter Unit...
Page 241: ......
Page 265: ......
Page 266: ...10 Direct Memory Access Unit...
Page 267: ......
Page 295: ...DIRECT MEMORY ACCESS UNIT 10 28...
Page 296: ...11 Math Coprocessing...
Page 297: ......
Page 314: ...12 ONCE Mode...
Page 315: ......
Page 318: ...A 80C186 Instruction Set Additions and Extensions...
Page 319: ......
Page 330: ...B Input Synchronization...
Page 331: ......
Page 334: ...C Instruction Set Descriptions...
Page 335: ......
Page 383: ...INSTRUCTION SET DESCRIPTIONS C 48...
Page 384: ...D Instruction Set Opcodes and Clock Cycles...
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Page 408: ...Index...
Page 409: ......