C-43
INSTRUCTION SET DESCRIPTIONS
SHR
Shift Logical Right:
SHR
dest, src
Shifts the bits in the destination
operand (byte or word) to the right by
the number of bits specified in the
count operand. Zeros are shifted in on
the left. If the sign bit retains its original
value, then OF is cleared.
Instruction Operands:
SHR reg, n
SHR mem, n
SHR reg, CL
SHR mem, CL
(temp)
←
count
do while (temp)
≠
0
(CF)
←
low-order bit of (dest)
(dest)
←
(dest) / 2
(temp)
←
(temp) – 1
if
count = 1
then
if
high-order bit of (dest)
≠
next-to-high-order bit of (dest)
then
(OF)
←
1
else
(OF)
←
0
else
(OF) undefined
AF ?
CF
ü
DF –
IF –
OF
ü
PF
ü
SF
ü
TF –
ZF
ü
STC
Set Carry Flag:
STC
Sets CF to 1.
Instruction Operands:
none
(CF)
←
1
AF –
CF
ü
DF –
IF –
OF –
PF –
SF –
TF –
ZF –
STD
Set Direction Flag:
STD
Sets DF to 1 causing the string instruc-
tions to auto-decrement the SI and/or
DI index registers.
Instruction Operands:
none
(DF)
←
1
AF –
CF –
DF
ü
IF –
OF –
PF –
SF –
TF –
ZF –
Table C-4. Instruction Set (Continued)
Name
Description
Operation
Flags
Affected
NOTE: The three symbols used in the Flags Affected column are defined as follows:
– the contents of the flag remain unchanged after the instruction is executed
? the contents of the flag is undefined after the instruction is executed
ü
the flag is updated after the instruction is executed
Summary of Contents for 80C186EA
Page 1: ...80C186EA 80C188EA Microprocessor User s Manual...
Page 2: ...80C186EA 80C188EA Microprocessor User s Manual 1995...
Page 19: ......
Page 20: ...1 Introduction...
Page 21: ......
Page 28: ...2 Overview of the 80C186 Family Architecture...
Page 29: ......
Page 79: ......
Page 80: ...3 Bus Interface Unit...
Page 81: ......
Page 129: ......
Page 130: ...4 Peripheral Control Block...
Page 131: ......
Page 139: ......
Page 140: ...5 ClockGenerationand Power Management...
Page 141: ......
Page 165: ......
Page 166: ...6 Chip Select Unit...
Page 167: ......
Page 190: ...7 Refresh Control Unit...
Page 191: ......
Page 205: ......
Page 206: ...8 Interrupt Control Unit...
Page 207: ......
Page 239: ...INTERRUPT CONTROL UNIT 8 32...
Page 240: ...9 Timer Counter Unit...
Page 241: ......
Page 265: ......
Page 266: ...10 Direct Memory Access Unit...
Page 267: ......
Page 295: ...DIRECT MEMORY ACCESS UNIT 10 28...
Page 296: ...11 Math Coprocessing...
Page 297: ......
Page 314: ...12 ONCE Mode...
Page 315: ......
Page 318: ...A 80C186 Instruction Set Additions and Extensions...
Page 319: ......
Page 330: ...B Input Synchronization...
Page 331: ......
Page 334: ...C Instruction Set Descriptions...
Page 335: ......
Page 383: ...INSTRUCTION SET DESCRIPTIONS C 48...
Page 384: ...D Instruction Set Opcodes and Clock Cycles...
Page 385: ......
Page 408: ...Index...
Page 409: ......