A-3
80C186 INSTRUCTION SET ADDITIONS AND EXTENSIONS
Figure A-1. Formal Definition of ENTER
ENTER treats a reentrant procedure as a procedure calling another procedure at the same lexical
level. A reentrant procedure can address only its own variables and variables of higher-level call-
ing procedures. ENTER ensures this by copying only stack frame pointers from higher-level pro-
cedures.
Block-structured high-level languages use lexical nesting levels to control access to variables of
previously nested procedures. For example, assume for Figure A-2 that Procedure A calls Proce-
dure B, which calls Procedure C, which calls Procedure D. Procedure C will have access to the
variables of Main and Procedure A, but not to those of Procedure B because Procedures C and B
operate at the same lexical nesting level.
The following is a summary of the variable access for Figure A-2.
1. Main has variables at fixed locations.
2. Procedure A can access only the fixed variables of Main.
3. Procedure B can access only the variables of Procedure A and Main.
Procedure B cannot access the variables of Procedure C or Procedure D.
4. Procedure C can access only the variables of Procedure A and Main.
Procedure C cannot access the variables of Procedure B or Procedure D.
5. Procedure D can access the variables of Procedure C, Procedure A and Main.
Procedure D cannot access the variables of Procedure B.
The following listing gives the formal definition of the
ENTER instruction for all cases.
LEVEL denotes the value of the second operand.
Push BP
Set a temporary value FRAME_PTR: = SP
If LEVEL > 0 then
Repeat (LEVEL - 1) times:
BP:=BP - 2
Push the word pointed to by BP
End Repeat
Push FRAME_PTR
End if
BP:=FRAME_PTR
SP:=SP - first operand
Summary of Contents for 80C186EA
Page 1: ...80C186EA 80C188EA Microprocessor User s Manual...
Page 2: ...80C186EA 80C188EA Microprocessor User s Manual 1995...
Page 19: ......
Page 20: ...1 Introduction...
Page 21: ......
Page 28: ...2 Overview of the 80C186 Family Architecture...
Page 29: ......
Page 79: ......
Page 80: ...3 Bus Interface Unit...
Page 81: ......
Page 129: ......
Page 130: ...4 Peripheral Control Block...
Page 131: ......
Page 139: ......
Page 140: ...5 ClockGenerationand Power Management...
Page 141: ......
Page 165: ......
Page 166: ...6 Chip Select Unit...
Page 167: ......
Page 190: ...7 Refresh Control Unit...
Page 191: ......
Page 205: ......
Page 206: ...8 Interrupt Control Unit...
Page 207: ......
Page 239: ...INTERRUPT CONTROL UNIT 8 32...
Page 240: ...9 Timer Counter Unit...
Page 241: ......
Page 265: ......
Page 266: ...10 Direct Memory Access Unit...
Page 267: ......
Page 295: ...DIRECT MEMORY ACCESS UNIT 10 28...
Page 296: ...11 Math Coprocessing...
Page 297: ......
Page 314: ...12 ONCE Mode...
Page 315: ......
Page 318: ...A 80C186 Instruction Set Additions and Extensions...
Page 319: ......
Page 330: ...B Input Synchronization...
Page 331: ......
Page 334: ...C Instruction Set Descriptions...
Page 335: ......
Page 383: ...INSTRUCTION SET DESCRIPTIONS C 48...
Page 384: ...D Instruction Set Opcodes and Clock Cycles...
Page 385: ......
Page 408: ...Index...
Page 409: ......