2-21
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
2.2.1.3 Bit Manipulation Instructions
There are three groups of instructions for manipulating bits within bytes and words. These three
groups are logical, shifts and rotates. Table 2-6 lists the bit manipulation instructions and their
functions.
Logical instructions include the Boolean operators NOT, AND, OR and exclusive OR (XOR), as
well as a TEST instruction. The TEST instruction sets the flags as a result of a Boolean AND op-
eration but does not alter either of its operands.
Individual bits in bytes and words can be shifted either arithmetically or logically. Up to 32 shifts
can be performed, according to the value of the count operand coded in the instruction. The count
can be specified as an immediate value or as a variable in the CL register. This allows the shift
count to be a supplied at execution time. Arithmetic shifts can be used to multiply and divide bi-
nary numbers by powers of two. Logical shifts can be used to isolate bits in bytes or words.
Table 2-5. Arithmetic Interpretation of 8-Bit Numbers
Hex
Bit Pattern
Unsigned
Binary
Signed
Binary
Unpacked
Decimal
Packed
Decimal
07
0 0 0 0 0 1 1 1
7
+7
7
7
89
1 0 0 0 1 0 0 1
137
–119
invalid
89
C5
1 1 0 0 0 1 0 1
197
–59
invalid
invalid
Table 2-6. Bit Manipulation Instructions
Logicals
NOT
“Not” byte or word
AND
“And” byte or word
OR
“Inclusive or” byte or word
XOR
“Exclusive or” byte or word
TEST
“Test” byte or word
Shifts
SHL/SAL
Shift logical/arithmetic left byte or word
SHR
Shift logical right byte or word
SAR
Shift arithmetic right byte or word
Rotates
ROL
Rotate left byte or word
ROR
Rotate right byte or word
RCL
Rotate through carry left byte or word
RCR
Rotate through carry right byte or word
Summary of Contents for 80C186EA
Page 1: ...80C186EA 80C188EA Microprocessor User s Manual...
Page 2: ...80C186EA 80C188EA Microprocessor User s Manual 1995...
Page 19: ......
Page 20: ...1 Introduction...
Page 21: ......
Page 28: ...2 Overview of the 80C186 Family Architecture...
Page 29: ......
Page 79: ......
Page 80: ...3 Bus Interface Unit...
Page 81: ......
Page 129: ......
Page 130: ...4 Peripheral Control Block...
Page 131: ......
Page 139: ......
Page 140: ...5 ClockGenerationand Power Management...
Page 141: ......
Page 165: ......
Page 166: ...6 Chip Select Unit...
Page 167: ......
Page 190: ...7 Refresh Control Unit...
Page 191: ......
Page 205: ......
Page 206: ...8 Interrupt Control Unit...
Page 207: ......
Page 239: ...INTERRUPT CONTROL UNIT 8 32...
Page 240: ...9 Timer Counter Unit...
Page 241: ......
Page 265: ......
Page 266: ...10 Direct Memory Access Unit...
Page 267: ......
Page 295: ...DIRECT MEMORY ACCESS UNIT 10 28...
Page 296: ...11 Math Coprocessing...
Page 297: ......
Page 314: ...12 ONCE Mode...
Page 315: ......
Page 318: ...A 80C186 Instruction Set Additions and Extensions...
Page 319: ......
Page 330: ...B Input Synchronization...
Page 331: ......
Page 334: ...C Instruction Set Descriptions...
Page 335: ......
Page 383: ...INSTRUCTION SET DESCRIPTIONS C 48...
Page 384: ...D Instruction Set Opcodes and Clock Cycles...
Page 385: ......
Page 408: ...Index...
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