ix
CONTENTS
10.2.1.8 Setting the Relative Priority of a Channel ....................................................10-19
10.2.2 Suspension of DMA Transfers ..............................................................................10-20
10.2.3 Initializing the DMA Unit ........................................................................................10-20
10.3 HARDWARE CONSIDERATIONS AND THE DMA UNIT ......................................... 10-20
10.3.1 DRQ Pin Timing Requirements .............................................................................10-20
10.3.2 DMA Latency ........................................................................................................10-21
10.3.3 DMA Transfer Rates .............................................................................................10-21
10.3.4 Generating a DMA Acknowledge ..........................................................................10-22
10.4 DMA UNIT EXAMPLES ............................................................................................. 10-22
CHAPTER 11
MATH COPROCESSING
11.1 OVERVIEW OF MATH COPROCESSING .................................................................. 11-1
11.2 AVAILABILITY OF MATH COPROCESSING.............................................................. 11-1
11.3 THE 80C187 MATH COPROCESSOR........................................................................ 11-2
11.3.1 80C187 Instruction Set ...........................................................................................11-2
11.3.1.1 Data Transfer Instructions .............................................................................11-3
11.3.1.2 Arithmetic Instructions ...................................................................................11-3
11.3.1.3 Comparison Instructions ................................................................................11-5
11.3.1.4 Transcendental Instructions ..........................................................................11-5
11.3.1.5 Constant Instructions .....................................................................................11-6
11.3.1.6 Processor Control Instructions ......................................................................11-6
11.3.2 80C187 Data Types ................................................................................................11-7
11.4 MICROPROCESSOR AND COPROCESSOR OPERATION...................................... 11-7
11.4.1 Clocking the 80C187 .............................................................................................11-10
11.4.2 Processor Bus Cycles Accessing the 80C187 ......................................................11-10
11.4.3 System Design Tips ..............................................................................................11-11
11.4.4 Exception Trapping ...............................................................................................11-13
11.5 EXAMPLE MATH COPROCESSOR ROUTINES...................................................... 11-13
CHAPTER 12
ONCE MODE
12.1 ENTERING/LEAVING ONCE MODE........................................................................... 12-1
APPENDIX A
80C186 INSTRUCTION SET ADDITIONS AND EXTENSIONS
A.1 80C186 INSTRUCTION SET ADDITIONS ................................................................... A-1
A.1.1 Data Transfer Instructions ...................................................................................... A-1
A.1.2 String Instructions ................................................................................................... A-2
A.1.3 High-Level Instructions ........................................................................................... A-2
A.2 80C186 INSTRUCTION SET ENHANCEMENTS......................................................... A-8
A.2.1 Data Transfer Instructions ...................................................................................... A-8
A.2.2 Arithmetic Instructions ............................................................................................ A-9
Summary of Contents for 80C186EA
Page 1: ...80C186EA 80C188EA Microprocessor User s Manual...
Page 2: ...80C186EA 80C188EA Microprocessor User s Manual 1995...
Page 19: ......
Page 20: ...1 Introduction...
Page 21: ......
Page 28: ...2 Overview of the 80C186 Family Architecture...
Page 29: ......
Page 79: ......
Page 80: ...3 Bus Interface Unit...
Page 81: ......
Page 129: ......
Page 130: ...4 Peripheral Control Block...
Page 131: ......
Page 139: ......
Page 140: ...5 ClockGenerationand Power Management...
Page 141: ......
Page 165: ......
Page 166: ...6 Chip Select Unit...
Page 167: ......
Page 190: ...7 Refresh Control Unit...
Page 191: ......
Page 205: ......
Page 206: ...8 Interrupt Control Unit...
Page 207: ......
Page 239: ...INTERRUPT CONTROL UNIT 8 32...
Page 240: ...9 Timer Counter Unit...
Page 241: ......
Page 265: ......
Page 266: ...10 Direct Memory Access Unit...
Page 267: ......
Page 295: ...DIRECT MEMORY ACCESS UNIT 10 28...
Page 296: ...11 Math Coprocessing...
Page 297: ......
Page 314: ...12 ONCE Mode...
Page 315: ......
Page 318: ...A 80C186 Instruction Set Additions and Extensions...
Page 319: ......
Page 330: ...B Input Synchronization...
Page 331: ......
Page 334: ...C Instruction Set Descriptions...
Page 335: ......
Page 383: ...INSTRUCTION SET DESCRIPTIONS C 48...
Page 384: ...D Instruction Set Opcodes and Clock Cycles...
Page 385: ......
Page 408: ...Index...
Page 409: ......