INSTRUCTION SET DESCRIPTIONS
C-20
INTO
Interrupt on Overflow:
INTO
Generates a software interrupt if the
overflow flag (OF) is set; otherwise
control proceeds to the following
instruction without activating an
interrupt procedure. INTO addresses
the target interrupt procedure (its type
is 4) through the interrupt pointer at
location 10H; it clears the TF and IF
flags and otherwise operates like INT.
INTO may be written following an
arithmetic or logical operation to
activate an interrupt procedure if
overflow occurs.
Instruction Operands:
none
if
(OF) = 1
then
(SP)
←
(SP) – 2
((SP) + 1:(SP))
←
FLAGS
(IF)
←
0
(TF)
←
0
(SP)
←
(SP) – 2
((SP) + 1:(SP))
←
(CS)
(CS)
←
(12H)
(SP)
←
(SP) – 2
((SP) + 1:(SP))
←
(IP)
(IP)
←
(10H)
AF –
CF –
DF –
IF –
OF –
PF –
SF –
TF –
ZF –
IRET
Interrupt Return:
IRET
Transfers control back to the point of
interruption by popping IP, CS, and the
flags from the stack. IRET thus affects
all flags by restoring them to previously
saved values. IRET is used to exit any
interrupt procedure, whether activated
by hardware or software.
Instruction Operands:
none
(IP)
←
((SP) + 1:(SP))
(SP)
←
(SP) + 2
(CS)
←
((SP) + 1:(SP))
(SP)
←
(SP) + 2
FLAGS
←
((SP) + 1:(SP))
(SP)
←
(SP) + 2
AF
ü
CF
ü
DF
ü
IF
ü
OF
ü
PF
ü
SF
ü
TF
ü
ZF
ü
JA
JNBE
Jump on Above:
Jump on Not Below or Equal:
JA disp8
JNBE
disp8
Transfers control to the target location
if the tested condition ((CF=0) or
(ZF=0)) is true.
Instruction Operands:
JA short-label
JNBE short-label
if
((CF) = 0) or ((ZF) = 0)
then
(IP)
←
(IP) + disp8 (sign-ext to 16 bits)
AF –
CF –
DF –
IF –
OF –
PF –
SF –
TF –
ZF –
Table C-4. Instruction Set (Continued)
Name
Description
Operation
Flags
Affected
NOTE: The three symbols used in the Flags Affected column are defined as follows:
– the contents of the flag remain unchanged after the instruction is executed
? the contents of the flag is undefined after the instruction is executed
ü
the flag is updated after the instruction is executed
Summary of Contents for 80C186EA
Page 1: ...80C186EA 80C188EA Microprocessor User s Manual...
Page 2: ...80C186EA 80C188EA Microprocessor User s Manual 1995...
Page 19: ......
Page 20: ...1 Introduction...
Page 21: ......
Page 28: ...2 Overview of the 80C186 Family Architecture...
Page 29: ......
Page 79: ......
Page 80: ...3 Bus Interface Unit...
Page 81: ......
Page 129: ......
Page 130: ...4 Peripheral Control Block...
Page 131: ......
Page 139: ......
Page 140: ...5 ClockGenerationand Power Management...
Page 141: ......
Page 165: ......
Page 166: ...6 Chip Select Unit...
Page 167: ......
Page 190: ...7 Refresh Control Unit...
Page 191: ......
Page 205: ......
Page 206: ...8 Interrupt Control Unit...
Page 207: ......
Page 239: ...INTERRUPT CONTROL UNIT 8 32...
Page 240: ...9 Timer Counter Unit...
Page 241: ......
Page 265: ......
Page 266: ...10 Direct Memory Access Unit...
Page 267: ......
Page 295: ...DIRECT MEMORY ACCESS UNIT 10 28...
Page 296: ...11 Math Coprocessing...
Page 297: ......
Page 314: ...12 ONCE Mode...
Page 315: ......
Page 318: ...A 80C186 Instruction Set Additions and Extensions...
Page 319: ......
Page 330: ...B Input Synchronization...
Page 331: ......
Page 334: ...C Instruction Set Descriptions...
Page 335: ......
Page 383: ...INSTRUCTION SET DESCRIPTIONS C 48...
Page 384: ...D Instruction Set Opcodes and Clock Cycles...
Page 385: ......
Page 408: ...Index...
Page 409: ......