OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
2-44
Breakpoint Interrupt — Type 3
The Breakpoint Interrupt is a single-byte version of the INT instruction. It is commonly used by
software debuggers to set breakpoints in RAM. Because the instruction is only one byte long, it
can substitute for any instruction.
Interrupt on Overflow — Type 4
The Interrupt on Overflow trap occurs if the Overflow Flag (OF) bit is set in the Processor Status
Word and the INT0 instruction is executed. Interrupt on Overflow is a common method for han-
dling arithmetic overflows conditionally.
Array Bounds Check — Type 5
An Array Bounds trap occurs when the array index is outside the array bounds during execution
of the BOUND instruction (see Appendix A, “80C186 Instruction Set Additions and Exten-
sions”).
Invalid Opcode — Type 6
Execution of an undefined opcode causes an Invalid Opcode trap.
Escape Opcode — Type 7
The Escape Opcode fault is used for floating point emulation. With 80C186 Modular Core family
members, this fault is enabled by setting the Escape Trap (ET) bit in the Relocation Register (see
Chapter 4, “Peripheral Control Block”). When a floating point instruction is executed with the
Escape Trap bit set, the Escape Opcode fault occurs, and the Escape Opcode service routine em-
ulates the floating point instruction. If the Escape Trap bit is cleared, the CPU sends the floating
point instruction to an external 80C187.
80C188 Modular Core Family members do not support the 80C187 interface and always generate
the Escape Opcode Fault. The 80C186EA will generate the Escape Opcode Fault regardless of
the state of the Escape Trap bit unless it is in Numerics Mode.
Numerics Coprocessor Fault — Type 16
The Numerics Coprocessor fault is caused by an external 80C187 numerics coprocessor. The
80C187 reports the exception by asserting the ERROR pin. The 80C186 Modular Core checks
the ERROR pin only when executing a numerics instruction. A Numerics Coprocessor Fault in-
dicates that the previous numerics instruction caused the exception. The 80C187 saves the ad-
dress of the floating point instruction that caused the exception. The return address pushed onto
the stack during the interrupt processing points to the numerics instruction that detected the ex-
ception. This way, the last numerics instruction can be restarted.
Summary of Contents for 80C186EA
Page 1: ...80C186EA 80C188EA Microprocessor User s Manual...
Page 2: ...80C186EA 80C188EA Microprocessor User s Manual 1995...
Page 19: ......
Page 20: ...1 Introduction...
Page 21: ......
Page 28: ...2 Overview of the 80C186 Family Architecture...
Page 29: ......
Page 79: ......
Page 80: ...3 Bus Interface Unit...
Page 81: ......
Page 129: ......
Page 130: ...4 Peripheral Control Block...
Page 131: ......
Page 139: ......
Page 140: ...5 ClockGenerationand Power Management...
Page 141: ......
Page 165: ......
Page 166: ...6 Chip Select Unit...
Page 167: ......
Page 190: ...7 Refresh Control Unit...
Page 191: ......
Page 205: ......
Page 206: ...8 Interrupt Control Unit...
Page 207: ......
Page 239: ...INTERRUPT CONTROL UNIT 8 32...
Page 240: ...9 Timer Counter Unit...
Page 241: ......
Page 265: ......
Page 266: ...10 Direct Memory Access Unit...
Page 267: ......
Page 295: ...DIRECT MEMORY ACCESS UNIT 10 28...
Page 296: ...11 Math Coprocessing...
Page 297: ......
Page 314: ...12 ONCE Mode...
Page 315: ......
Page 318: ...A 80C186 Instruction Set Additions and Extensions...
Page 319: ......
Page 330: ...B Input Synchronization...
Page 331: ......
Page 334: ...C Instruction Set Descriptions...
Page 335: ......
Page 383: ...INSTRUCTION SET DESCRIPTIONS C 48...
Page 384: ...D Instruction Set Opcodes and Clock Cycles...
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Page 408: ...Index...
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