Intel 80C186EA, User Manual

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11-11
MATH COPROCESSING
Bus cycles involving the 80C187 Math Coprocessor behave exactly like other I/O bus cycles with
respect to the processor’s control pins. See “System Design Tips” for information on integrating
the 80C187 into the overall system.
11.4.3 System Design Tips
All 80C187 operations require that bus ready be asserted. The simplest way to return the ready
indication is through hardware connected to the processor’s external ready pin. If you program a
chip-select to cover the math coprocessor port addresses, its ready programming is in force and
can provide bus ready for coprocessor accesses. The user must verify that there are no conflicts
from other hardware connected to that chip-select pin.
A chip-select pin goes active on 80C187 accesses if you program it for a range including the math
coprocessor I/O ports. The converse is not true — a non-80C187 access cannot activate NCS (nu-
merics coprocessor select), regardless of programming.
In a buffered system, it is customary to place the 80C187 on the local bus. Since DTR and DEN
function normally during 80C187 transfers, you must qualify DEN with NCS (see Figure 11-3).
Otherwise, contention between the 80C187 and the transceivers occurs on read cycles to the
80C187.
The microprocessor’s local bus is available to the integrated peripherals during numerics execu-
tion whenever the CPU is not communicating with the 80C187. The idle bus allows the processor
to intersperse DRAM refresh cycles and DMA cycles with accesses to the 80C187.
The microprocessor’s local bus is available to alternate bus masters during execution of numerics
instructions when the CPU does not need it. Bus cycles driven by alternate masters (via the
HOLD/HLDA protocol) can suspend coprocessor bus cycles for an indefinite period.
The programmer can lock 80C187 instructions. The CPU asserts the LOCK pin for the entire du-
ration of a numerics instruction, monopolizing the bus for a very long time.