Intel 80C186EA, User Manual

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10-7
DIRECT MEMORY ACCESS UNIT
10.1.6 DMA Transfer Counts
Each DMA Unit maintains a programmable 16-bit transfer count value that controls the total
number of transfers the channel runs. The transfer count is decremented by one after each transfer
(regardless of data size). The DMA channel can be programmed to terminate transfers when the
transfer count reaches zero (also referred to as terminal count).
10.1.7 Termination and Suspension of DMA Transfers
When DMA transfers for a channel are terminated, no further DMA requests for that channel will
be granted until the channel is re-started by direct programming. A suspended DMA transfer tem-
porarily disables transfers in order to perform a specific task. A suspended DMA channel does
not need to be re-started by direct programming.
10.1.7.1 Termination at Terminal Count
When programmed to terminate on terminal count, the DMA channel disarms itself when the
transfer count value reaches zero. No further DMA transfers take place on the channel until it is
re-armed by direct programming. Unsynchronized transfers always terminate when the transfer
count reaches zero, regardless of programming.
10.1.7.2 Software Termination
A DMA channel can be disarmed by direct programming. Any DMA transfer that is in progress
will complete, but no further transfers are run until the channel is re-armed.
10.1.7.3 Suspension of DMA During NMI
DMA transfers are inhibited during the service of Non-Maskable Interrupts (NMI). DMA activity
is halted in order to give the CPU full command of the system bus during the NMI service. Exit
from the NMI via an IRET instruction re-enables the DMA Unit. DMA transfers can be enabled
during an NMI service routine by the system software.
10.1.7.4 Software Suspension
DMA transfers can be temporarily suspended by direct programming. In time-critical sections of
code, such as interrupt handlers, it may be necessary to shut off DMA activity temporarily in or-
der to give the CPU total control of the bus.