Intel 80C186EA, User Manual

Page: 160 / 417

5-19
CLOCK GENERATION AND POWER MANAGEMENT
The first step in determining the proper C
PD
value is startup time characterization for the crystal
oscillator circuit. This step can be done with a storage oscilloscope if you compensate for scope
probe loading effects. Characterize startup over the full range of operating voltages and temper-
atures. The oscillator starts up on the order of a couple of milliseconds. After determining the os-
cillator startup time, refer to “PDTMR Pin Delay Calculation” in the data sheet. Multiply the
startup time (in seconds) by the given constant to get the C
PD
value. Typical values are less than
1µF.
If the design uses an external oscillator instead of a crystal, the external oscillator continues run-
ning during Powerdown mode. Leave the PDTMR pin unconnected and the processor can exit
Powerdown mode immediately.
5.2.3 Power-Save Mode
In addition to Idle and Powerdown modes, Power-Save mode provides another means for reduc-
ing operating current. Power-Save mode enables a programmable clock divider in the clock gen-
eration circuit. This divider operates in addition to the divide-by-two counter (see Figure 5-1 on
page 5-1)
NOTE
Power-Save mode can be used to stretch bus cycles as an alternative to wait
states.
Possible clock divisor settings are 1 (undivided), 4, 8 and 16. The divided frequency feeds the
core, the integrated peripherals and CLKOUT. The processor operates at the divided clock rate
exactly as if the crystal or external oscillator frequency were lower by the same amount. Since
the processor is static, a lower limit clock frequency does not apply.
The advantage of Power-Save mode over Idle and Powerdown modes is that operation of both
the core and the integrated peripherals can continue. However, it may be necessary to reprogram
integrated peripherals such as the Timer Counter Unit and the Refresh Control Unit to compen-
sate for the overall reduced clock rate.
5.2.3.1 Entering Power-Save Mode
The Power-Save Register (Figure 5-14) controls Power-Save mode operation. The lower two bits
select the divisor. When program execution sets the PSEN bit, the processor enters Power-Save
mode. The internal clock frequency changes at the falling edge of T3 of the write to the Power-
Save Register. CLKOUT changes simultaneously and does not glitch. Figure 5-15 illustrates the
change at CLKOUT.