Fujitsu MB90460 Series, Hardware Manual, Page: 92 / 739

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CHAPTER 4 RESET
4.5 Reset Cause Bits
A reset cause can be identified by reading the watchdog timer control register (WDTC).
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Reset Cause Bits
As shown in Figure 4.5-1 , a flip-flop is associated with each reset cause. The contents of the flip-flops are
obtained by reading the watchdog timer control register (WDTC). If it is necessary to identify the cause of
a reset after the reset has been cleared, the value read from the WDTC should be processed by the software
and a branch made to the appropriate program.
Figure 4.5-1 Block Diagram of Reset Cause Bits
F / F
F / F F / F F / F
RSTX = L
S
S S S R R
R
R
Q
Q Q Q
Pin
Without periodic clear
RST bit set Power-on
Power-on
External reset
Watchdog timer LPMCR RST bit
Delay
WDTC register
WDTC register read
F
2
MC-16LX internal bus
circuit
write detection circuit detection circuit
request detection
circuit
reset detection circuit
Watchdog timer
control register
(WDTC)
S : Set
R : Reset
Q : Output
F/F : Flip Flop
:
RSTX