Fujitsu MB90460 Series, Hardware Manual, Page: 424 / 739

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CHAPTER 15 MULTI-PULSE GENERATOR
15.6.3 Operation of Output Data Buffer Register
The Output Data Buffer Register (OPDBR) is composed of twelve registers. By loading
different OPDBR register into the Output Data Register (OPDR), various kind of
waveform is output at the Multi-pulse Generator Output (OPT5 to OPT0).
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Operation of Output Data Buffer Register
The data in the Output Data Buffer Register (OPDBR) whose address specified by the BNKF, RDA2 to
RDA0 bits is transferred to the Output Data Register (OPDR) at the write timing generated by the Data
Write Control Unit.
The BNKF, RDA2 to RDA0 bits of the Output Data Buffer Register (OPDBR) decide the order of data
transfer to the Output Data Register (OPDR), and the OPx1/OPx0 bits decide the shape of the output
waveform. The output waveform is updated automatically as long as the write timing (WTO) is generated.
An example of setting the Output Data Buffer Register (OPDBR) is shown in Table 15.6-3.
Table 15.6-3 Output Data Buffer Register (OPDBR)
No. 0 1 2 3 4 5 6 7 8 9 A
BNKF 0 0 0 0 0 1 0 X X 0 1
RDA2 1 1 0 0 1 0 0 X X 1 0
RDA1 0 0 1 0 1 1 1 X X 0 1
RDA0 0 1 1 1 0 0 0 X X 0 1
OP51 0 0 0 1 0 0 0 X X 0 0
OP50 0 0 1 1 0 0 0 X X 0 1
OP41 1 0 0 0 0 1 0 X X 0 0
OP40 1 1 0 0 0 1 0 X X 1 0
OP31 0 0 0 0 0 0 1 X X 0 0
OP30 0 0 0 0 1 0 1 X X 0 0
OP21 0 0 0 0 1 0 0 X X 0 0
OP20 1 0 0 0 1 1 0 X X 0 0
OP11 0 0 1 0 0 0 0 X X 0 1
OP10 0 0 1 0 0 0 1 X X 0 1
OP01 0 1 0 0 0 0 0 X X 1 0
OP00 0 1 0 1 0 0 0 X X 1 0
OPBDR No. Sequence 4 5 3 1 6 A 2 X X 4 B
OPT5 Output L L PPG H L L L X X L PPG
OPT4 Output H PPG L L L H L X X PPG L
OPT3 Output L L L L PPG L H X X L L
OPT2 Output PPG L L L H PPG L X X L L
OPT1 Output L L H L L L PPG X X L H
OPT0 Output L H L PPG L L L X X H L