Fujitsu MB90460 Series, Hardware Manual, Page: 488 / 739

469
CHAPTER 17 UART
■
UART Interrupt and EI
2
OS
Table 17.1-2 UART Operation Mode
Operation mode
Data length
Synchronization
on mode
Stop bit length
When parity is
disabled
When parity is
enabled
0 Normal mode 7 or 8 bits Asynchronous
1 or 2 bits *
2
1 Multiprocessor
8+1*
1
bits
– Asynchronous
2 Normal mode 8 bits – Synchronous None
– : Setting not possible.
*1: "+1" indicates the address/data selection bit (A/D) for communication control.
*2: During reception, only one stop bit can be detected.
Table 17.1-3 UART Interrupt and EI
2
OS
Interrupt cause
Interrupt
number
Interrupt control register Vector table address
EI²OS
Register
name
Address Lower Upper Bank
UART1 reception
interrupt
#37(25
H
)
ICR13
0000BD
H
FFFF68
H
FFFF69
H
FFFF6A
H
UART1 transmission
interrupt
#38(26
H
)
ICR13
0000BD
H
FFFF64
H
FFFF65
H
FFFF66
H
∆
UART0 reception
interrupt
#39(27
H
)
ICR14
0000BE
H
FFFF60
H
FFFF61
H
FFFF62
H
UART0 transmission
interrupt
#40(28
H
)
ICR14
0000BE
H
FFFF5C
H
FFFF5D
H
FFFF5E
H
∆
: Provided with a function that detects a UART reception error and stops EI
2
OS
∆
: Usable when ICR13 and ICR14 or interrupt causes that share an interrupt vector are not used