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APPENDIX  

Table B.9-10  ea Instruction 5 (First Byte = 74

H

)

00

10

20

30

40

50

60

70

80

9

0

A

0

B0

C0

D0

E0

F0

+0

ADD

A,

 R0

ADD  

   

 A,

@RW0+d8

SUB

A,

 R

0

SUB

    

  A

,

@RW0+d8

ADDC

A, R0

ADDC  

  

A,

@R

W

0

+

d

8

CMP

A,

 R0

CMP  

  

  A,

@RW0+d8

AND

A,

 R0

A

ND   

  

  A

,

@RW0+d8

OR

A,

 R

0

OR 

   

  

   

 A

,

@RW0+d

8

XO

R

A,

 R0

XOR  

   

 A,

@R

W

0

+

d

8

DBNZ

R0

, r

DB

NZ

   

 @

RW0

+

d8,

 r

+1

ADD

A,

 R1

ADD  

   

 A,

@RW1+d8

SUB

A,

 R

1

SUB

    

  A

,

@RW1+d8

ADDC

A, R1

ADDC  

  

A,

@R

W

1

+

d

8

CMP

A,

 R1

CMP  

  

  A,

@RW1+d8

AND

A,

 R1

A

ND   

  

  A

,

@RW1+d8

OR

A,

 R

1

OR 

   

  

   

 A

,

@RW1+d

8

XO

R

A,

 R1

XOR  

   

 A,

@R

W

1

+

d

8

DBNZ

R1

, r

DB

NZ

   

 @

RW1

+

d8,

 r

+2

ADD

A,

 R2

ADD  

   

 A,

@RW2+d8

SUB

A,

 R

2

SUB

    

  A

,

@RW2+d8

ADDC

A, R2

ADDC  

  

A,

@R

W

2

+

d

8

CMP

A,

 R2

CMP  

  

  A,

@RW2+d8

AND

A,

 R2

A

ND   

  

  A

,

@RW2+d8

OR

A,

 R

2

OR 

   

  

   

 A

,

@RW2+d

8

XO

R

A,

 R2

XOR  

   

 A,

@R

W

2

+

d

8

DBNZ

R2

, r

DB

NZ

   

 @

RW2

+

d8,

 r

+3

ADD

A,

 R3

ADD  

   

 A,

@RW3+d8

SUB

A,

 R

3

SUB

    

  A

,

@RW3+d8

ADDC

A, R3

ADDC  

  

A,

@R

W

3

+

d

8

CMP

A,

 R3

CMP  

  

  A,

@RW3+d8

AND

A,

 R3

A

ND   

  

  A

,

@RW3+d8

OR

A,

 R

3

OR 

   

  

   

 A

,

@RW3+d

8

XO

R

A,

 R3

XOR  

   

 A,

@R

W

3

+

d

8

DBNZ

R3

, r

DB

NZ

   

 @

RW3

+

d8,

 r

+4

ADD

A,

 R4

ADD  

   

 A,

@RW4+d8

SUB

A,

 R

4

SUB

    

  A

,

@RW4+d8

ADDC

A, R4

ADDC  

  

A,

@R

W

4

+

d

8

CMP

A,

 R4

CMP  

  

  A,

@RW4+d8

AND

A,

 R4

A

ND   

  

  A

,

@RW4+d8

OR

A,

 R

4

OR 

   

  

   

 A

,

@RW4+d

8

XO

R

A,

 R4

XOR  

   

 A,

@R

W

4

+

d

8

DBNZ

R4

, r

DB

NZ

   

 @

RW4

+

d8,

 r

+5

ADD

A,

 R5

ADD  

   

 A,

@RW5+d8

SUB

A,

 R

5

SUB

    

  A

,

@RW5+d8

ADDC

A, R5

ADDC  

  

A,

@R

W

5

+

d

8

CMP

A,

 R5

CMP  

  

  A,

@RW5+d8

AND

A,

 R5

A

ND   

  

  A

,

@RW5+d8

OR

A,

 R

5

OR 

   

  

   

 A

,

@RW5+d

8

XO

R

A,

 R5

XOR  

   

 A,

@R

W

5

+

d

8

DBNZ

R5

, r

DB

NZ

   

 @

RW5

+

d8,

 r

+6

ADD

A,

 R6

ADD  

   

 A,

@RW6+d8

SUB

A,

 R

6

SUB

    

  A

,

@RW6+d8

ADDC

A, R6

ADDC  

  

A,

@R

W

6

+

d

8

CMP

A,

 R6

CMP  

  

  A,

@RW6+d8

AND

A,

 R6

A

ND   

  

  A

,

@RW6+d8

OR

A,

 R

6

OR 

   

  

   

 A

,

@RW6+d

8

XO

R

A,

 R6

XOR  

   

 A,

@R

W

6

+

d

8

DBNZ

R6

, r

DB

NZ

   

 @

RW6

+

d8,

 r

+7

ADD

A,

 R7

ADD  

   

 A,

@RW7+d8

SUB

A,

 R

7

SUB

    

  A

,

@RW7+d8

ADDC

A, R7

ADDC  

  

A,

@R

W

7

+

d

8

CMP

A,

 R7

CMP  

  

  A,

@RW7+d8

AND

A,

 R7

A

ND   

  

  A

,

@RW7+d8

OR

A,

 R

7

OR 

   

  

   

 A

,

@RW7+d

8

XO

R

A,

 R7

XOR  

   

 A,

@R

W

7

+

d

8

DBNZ

R7

, r

DB

NZ

   

 @

RW7

+

d8,

 r

+8

ADD

A,

@R

W

0

ADD

   

   A,

@R

W0+d

16

SUB

A,

@RW0

SU

B    

  A,

@R

W0+d1

6

ADDC

A,

@

R

W

0

ADDC

  

  A,

@

R

W

0

+d16

CMP

A,

@

R

W0

C

M

P    

  A,

@

R

W

0+

d16

AND

A,

@RW0

AND

    

   A,

@R

W0+d1

6

OR

A,

@

R

W

0

OR

       

   A,

@R

W0

+d16

XO

R

A,

@

R

W

0

XO

R 

     A,

@

R

W

0

+d16

DBNZ

@R

W0

, r

DB

NZ

  @

R

W

0+d16,

 r

+9

ADD

A,

@R

W

1

ADD

   

   A,

@R

W1+d

16

SUB

A,

@RW1

SU

B    

  A,

@R

W1+d1

6

ADDC

A,

@

R

W

1

ADDC

  

  A,

@

R

W

1

+d16

CMP

A,

@

R

W1

C

M

P    

  A,

@

R

W

1+

d16

AND

A,

@RW1

AND

    

   A,

@R

W1+d1

6

OR

A,

@

R

W

1

OR

       

   A,

@R

W1

+d16

XO

R

A,

@

R

W

1

XO

R 

     A,

@

R

W

1

+d16

DBNZ

@R

W1

, r

DB

NZ

  @

R

W

1+d16,

 r

+A

ADD

A,

@R

W

2

ADD

   

   A,

@R

W2+d

16

SUB

A,

@RW2

SU

B    

  A,

@R

W2+d1

6

ADDC

A,

@

R

W

2

ADDC

  

  A,

@

R

W

2

+d16

CMP

A,

@

R

W2

C

M

P    

  A,

@

R

W

2+

d16

AND

A,

@RW2

AND

    

   A,

@R

W2+d1

6

OR

A,

@

R

W

2

OR

       

   A,

@R

W2

+d16

XO

R

A,

@

R

W

2

XO

R 

     A,

@

R

W

2

+d16

DBNZ

@R

W2

, r

DB

NZ

  @

R

W

2+d16,

 r

+B

ADD

A,

@R

W

3

ADD

   

   A,

@R

W3+d

16

SUB

A,

@RW3

SU

B    

  A,

@R

W3+d1

6

ADDC

A,

@

R

W

3

ADDC

  

  A,

@

R

W

3

+d16

CMP

A,

@

R

W3

C

M

P    

  A,

@

R

W

3+

d16

AND

A,

@RW3

AND

    

   A,

@R

W3+d1

6

OR

A,

@

R

W

3

OR

       

   A,

@R

W3

+d16

XO

R

A,

@

R

W

3

XO

R 

     A,

@

R

W

3

+d16

DBNZ

@R

W3

, r

DB

NZ

  @

R

W

3+d16,

 r

+C

ADD

A,

@R

W

0+

ADD      A,

@R

W0

+

R

W

7

SUB

A,

@RW0+

SUB     

 A,

@RW

0+R

W7

ADDC

A

,@RW0+

A

DDC    A,

@RW0+

R

W7

CMP

A,

@

R

W0

+

CMP     

 A,

@RW0

+

R

W7

AND

A,

@RW0+

AND       

A

,

@R

W0

+R

W

7

OR

A,@

R

W

0

+

O

R

      

    A,

@

R

W0+

R

W7

XO

R

A

,@RW0+

XO

R     

 A,

@RW0+

R

W7

DBNZ

@R

W0

+, r

DB

N

Z

  @R

W0

+

R

W7

, r

+D

ADD

A,

@R

W

1+

ADD      A,

@R

W1

+

R

W

7

SUB

A,

@RW1+

SUB     

 A,

@RW

1+R

W7

ADDC

A

,@RW1+

A

DDC    A,

@RW1+

R

W7

CMP

A,

@

R

W1

+

CMP     

 A,

@RW1

+

R

W7

AND

A,

@RW1+

AND       

A

,

@R

W1

+R

W

7

OR

A,@

R

W

1

+

O

R

      

    A,

@

R

W1+

R

W7

XO

R

A

,@RW1+

XO

R     

 A,

@RW1+

R

W7

DBNZ

@R

W1

+, r

DB

N

Z

  @R

W1

+

R

W7

, r

+E

ADD

A,

@R

W

2+

ADD  

   

 A,

@PC+d1

6

SUB

A,

@RW2+

SUB

    

  A

,

@PC+d

1

6

ADDC

A

,@RW2+

ADDC  

  

A,

@

P

C+d16

CMP

A,

@

R

W2

+

CMP  

  

  A,

@PC+d16

AND

A,

@RW2+

A

ND   

  

  A

,

@PC+d1

6

OR

A,@

R

W

2

+

OR 

   

  

   

 A

,

@P

C

+

d

16,

XO

R

A

,@RW2+

XOR  

   

 A,

@

P

C+d16

DBNZ

@R

W2

+, r

DB

NZ

   

 @

P

C

+d16,

 r

+F

ADD

A,

@R

W

3+

ADD

A

, ad

dr16

SUB

A,

@RW3+

SU

B

 

A,

 a

ddr16

ADDC

A

,@RW3+

ADDC

A,

 addr1

6

CMP

A,

@

R

W3

+

CMP

A

, add

r16

AND

A,

@RW3+

AND

A,

 ad

dr16

OR

A,@

R

W

3

+

OR

A,

 a

ddr1

6

XO

R

A

,@RW3+

XOR

A,

 ad

dr16

DBNZ

@R

W3

+, r

DB

NZ

addr1

6,

 r

Summary of Contents for MB90460 Series

Page 1: ...The following document contains information on Cypress products ...

Page 2: ...FUJITSU MICROELECTRONICS CONTROLLER MANUAL F2 MC 16LX 16 BIT MICROCONTROLLER MB90460 465 Series HARDWARE MANUAL CM44 10120 4E ...

Page 3: ......

Page 4: ...roller supports is shown in the following homepage Be sure to refer to the Check Sheet for the latest cautions on development Check Sheet is seen at the following support page Check Sheet lists the minimal requirement items to be checked to prevent problems beforehand in system development http edevice fujitsu com micom en support ...

Page 5: ......

Page 6: ...features and basic specifications of the MB90460 465 series Chapter 2 Notes on Handling Devices This chapter describes notes on Handling Devices Chapter 3 CPU This chapter describes the memory space of the MB90460 465 series Chapter 4 Reset This chapter describes the reset function of the MB90460 465 series Chapter 5 Clock This chapter describes the clocks of the MB90460 465 series Chapter 6 Low P...

Page 7: ...apter 19 Delayed Interrupt Generator Module This chapter describes the functions and operation of the MB90460 465 series delayed interrupt generator module Chapter 20 8 10 bit A D Converter This chapter describes the functions and operation of the MB90460 465 series 8 10 bit A D Converter Chapter 21 ROM Correction Function This chapter describes the functions and operation of the MB90460 465 serie...

Page 8: ...rmation contained herein The products described in this document are designed developed and manufactured as contemplated for general use including without limitation ordinary industrial use general office use personal use and household use but are not designed developed and manufactured as contemplated 1 for use accompanying fatal risks or dangers that unless extremely high safety is secured could...

Page 9: ...iv ...

Page 10: ...ulti byte Data 37 3 6 Registers 39 3 7 Dedicated Registers 40 3 7 1 Accumulator A 42 3 7 2 Stack Pointers USP SSP 45 3 7 3 Processor Status PS 47 3 7 4 Condition Code Register PS CCR 48 3 7 5 Register Bank Pointer PS RP 50 3 7 6 Interrupt Level Mask Register PS ILM 51 3 7 7 Program Counter PC 52 3 7 8 Direct Page Register DPR 53 3 7 9 Bank Registers PCB DTB USB SSB ADB 54 3 8 General purpose Regis...

Page 11: ...7 1 Interrupt 114 7 2 Interrupt Causes and Interrupt Vectors 116 7 3 Interrupt Control Registers and Peripheral Functions 119 7 3 1 Interrupt Control Registers ICR00 to ICR15 121 7 3 2 Interrupt Control Register Functions 123 7 4 Hardware Interrupt 126 7 4 1 Operation of Hardware Interrupt 129 7 4 2 Processing for Interrupt Operation 131 7 4 3 Procedure for using Hardware Interrupt 132 7 4 4 Multi...

Page 12: ...193 9 8 1 Port 5 Registers PDR5 DDR5 and ADER 195 9 8 2 Operation of Port 5 196 9 9 Port 6 198 9 9 1 Port 6 Registers PDR6 and DDR6 200 9 9 2 Operation of Port 6 201 9 10 Sample I O Port Program 203 CHAPTER 10 TIME BASE TIMER 205 10 1 Overview of the Time base Timer 206 10 2 Configuration of the Time base Timer 208 10 3 Time base Timer Control Register TBTC 209 10 4 Time base Timer Interrupts 211 ...

Page 13: ... 264 13 4 2 PPG Period Setting Buffer Register PCSR0 to PCSR2 265 13 4 3 PPG Duty Setting Buffer Register PDUT0 to PDUT2 266 13 4 4 PPG Control Status Register PCNTL0 to PCNTL2 PCNTH0 to PCNTH2 267 13 5 16 bit PPG Timer Interrupts 271 13 6 Operation of 16 bit PPG Timer 273 13 7 Usage Notes on the 16 bit PPG Timer 276 13 8 Sample Programs for the 16 bit PPG Timer 277 CHAPTER 14 MULTI FUNCTIONAL TIM...

Page 14: ...ontrol Register NCCR 392 15 5 Multi pulse Generator Interrupts 394 15 6 Operation of Multi pulse Generator 397 15 6 1 Operation of Position Detection 399 15 6 2 Operation of Data Write Control Unit 401 15 6 3 Operation of Output Data Buffer Register 405 15 6 4 Operation of Data Transfer of Output Data Register 407 15 6 5 Operation of DTTI1 Input Control 421 15 6 6 Operation of Noise Cancellation F...

Page 15: ...Asynchronous Mode Operation Modes 0 and 1 500 17 7 2 Operation in Synchronous Mode Operation Mode 2 502 17 7 3 Bidirectional Communication Function Normal Mode 504 17 7 4 Master slave Communication Function Multiprocessor Mode 506 17 8 Usage Notes on UART 509 17 9 Sample Program for UART 510 CHAPTER 18 DTP EXTERNAL INTERRUPT CIRCUIT 513 18 1 Overview of the DTP External Interrupt Circuit 514 18 2 ...

Page 16: ... Function 572 21 2 Block Diagram of ROM Correction Function 573 21 3 ROM Correction Function Registers 574 21 3 1 Program Aaddress Detection Register PADR0 PADR1 575 21 3 2 Program Address Detection Control Status Register PACSR 576 21 4 Operation of the ROM Correction Function 578 21 5 Example of Using ROM Correction Function 579 CHAPTER 22 ROM MIRRORING FUNCTION SELECTION MODULE 583 22 1 Overvie...

Page 17: ...4 3 Example of Connection for Serial Writing When Power Supplied from Writer 620 24 4 Example of Minimum Connection with Flash Microcontroller Programmer When Power Supplied by User 622 24 5 Example of Minimum Connection with Flash Microcontroller Programmer When Power Supplied from Writer 624 APPENDIX 627 APPENDIX A I O MAP 628 APPENDIX B Instructions 635 B 1 Instruction Types 636 B 2 Addressing ...

Page 18: ...e next count clock is added 521 CHAPTER 18 DTP EXTERNAL INTERRUPT CIRCUIT 18 4 1 DTP interrupt Cause Register EIRR DTP interrupt Cause Register EIRR is changed Notes is added 522 CHAPTER 18 DTP EXTERNAL INTERRUPT CIRCUIT 18 4 2 DTP interrupt Enable Register ENIR DTP interrupt Enable Register ENIR is changed Note is added 525 CHAPTER 18 DTP EXTERNAL INTERRUPT CIRCUIT 18 5 Operation of the DTP Exter...

Page 19: ...tion is changed up to 15 µs up to 20 µs The sector deletion temporary stop command must be executed 20 µs or more after the sector deletion command or sector deletion restart command is issued 616 CHAPTER 24 EXAMPLE OF F2MC 16LX MB90F462 F462A F463A CONNECTION FOR SERIAL WRITING 24 1 Standard Configuration for Serial On board Writing Fujitsu Standard Table 24 1 1 is changed Page Section Change Res...

Page 20: ...res and basic specifications of the MB90460 465 series 1 1 MB90460 465 Series Features 1 2 MB90460 465 Series Product line up 1 3 Block Diagram of MB90460 465 Series 1 4 Pin Assignment 1 5 Package Dimensions 1 6 I O Pins and Pin Functions 1 7 I O Circuit Types ...

Page 21: ...y at high speed MB90460 465 Series Features Clock Embedded PLL clock multiplication circuit Operating clock PLL clock can selected from divided by 2 of oscillation or one to four times the oscillation at oscillation of 4 MHz 4 MHz to 16 MHz Minimum instruction execution time of 62 5 ns at oscillation of 4 MHz four times the PLL clock operation at Vcc of 5 0 V CPU addressing space of 16 Mbytes Inte...

Page 22: ...scillation is stopped CPU intermittent operation mode Package LQFP 64 FPT 64P M09 0 65 mm pitch QFP 64 FPT 64P M06 1 00 mm pitch SDIP 64 DIP 64P M01 1 78 mm pitch Process CMOS technology Internal Peripheral Features I O port Maximum of 51 ports 18 bit time base counter watchdog timer 1 channel Watchdog timer 1 channel PWC 2 channels MB90460 series 1 channel MB90465 series 16 bit reload timer 1 cha...

Page 23: ...h buffer and compare clear function not present in MB90465 series UART 2 channels With full duplex double buffer 8 bit length Clock asynchronized or clock synchronized transmission with start and stop bits can be selectively used DTP External interrupt circuit 8 channels A module for starting extended intelligent I O service EI2OS and generating an external interrupt triggered by an external input...

Page 24: ...ulti pulse generator MB90460 series only or individually 16 bit PPG timer PPG timer 3 channels 2 channels PWM mode or single shot mode selectable Can be worked with multi functional timer multi pulse generator MB90460 series only or individually Multi functional timer for AC DC motor control 16 bit free run timer with up or up down mode selection and buffer 1 channel 16 bit output compare 6 channe...

Page 25: ...T 64P M09 0 65 mm pitch QFP 64 FPT 64P M06 1 00 mm pitch SDIP 64 DIP 64P M01 1 78 mm pitch Operating voltage 5V 10 16 MHz Table 1 2 1 MB90460 465 Series Product Line up 2 2 MB90V460 MB90F462 MB90F462A MB90F463A MB90462 MB90467 Part number Parameter ...

Page 26: ...RTO5 Z P10 INT0 DTTI0 P50 AN0 P51 AN1 P52 AN2 P53 AN3 P54 AN4 P55 AN5 P56 AN6 P57 AN7 CPU F2MC 16LX family core Delayed interrupt generator Time base timer AVCC AVR AVSS A D converter 8 8 10 bit Reset circuit Watchdog timer Vss x 2 Vcc x 1 MD0 2 C Other pins 16 bit PPG Ch 0 16 bit input capture Ch 0 to Ch 3 16 bit free run timer 16 bit output Ch 0 to Ch 5 compare Waveform generator Multi functiona...

Page 27: ... P23 PWO1 P22 PWI1 P21 TO1 P20 TIN1 P17 FRCK P16 INT6 TO0 P15 INT5 TIN0 P14 INT4 P13 INT3 P12 INT2 DTTI1 2 P11 INT1 P10 INT0 DTTI0 P07 PWO0 2 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 RSTX MD1 MD2 X0 X1 V SS P00 1 OPT0 2 P01 1 OPT1 2 P02 1 OPT2 2 P03 1 OPT3 2 P04 1 OPT4 2 P05 1 OPT5 2 P06 1 PWI0 2 20 21 22 23 24 25 26 27 28 29 30 31 32 TOP VIEW...

Page 28: ...2 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 P27 IN3 P26 IN2 P25 IN1 P24 IN0 P23 PWO1 P22 PWI1 P21 TO1 P20 TIN1 P17 FRCK P16 INT6 TO0 P15 INT5 TIN0 P14 INT4 P13 INT3 P12 INT2 DTTI1 2 P11 INT1 P10 INT0 DTTI0 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P44 SNI1 2 P43 SNI0 2 P42 SCK0 P41 SOT0 P40 SIN0 P37 PPG0 P36 PPG1 2 C V cc P35 1 RTO5 Z P34 1 RTO4 W P33 1 RTO3 Y P32 1 RTO2 V P31 1 RTO1 X...

Page 29: ...1 X P30 1 RTO0 U VSS P27 IN3 P26 IN2 P25 IN1 P24 IN0 P23 PWO1 P22 PWI1 P21 TO1 P20 TIN1 P17 FRCK P16 INT6 TO0 P15 INT5 TIN0 P14 INT4 P13 INT3 P12 INT2 DTTI1 2 P11 INT1 P10 INT0 DTTI0 P07 PWO0 2 P06 PWI0 2 P05 1 OPT5 2 P04 1 OPT4 2 P03 1 OPT3 2 P02 1 OPT2 2 P01 1 OPT1 2 P00 1 OPT0 2 TOP VIEW 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 ...

Page 30: ... width package length 17 58 mm Sealing method Plastic mold Mounting height 5 65 mm MAX 64 pin plastic SH DIP DIP 64P M01 DIP 64P M01 C 2001 2008 FUJITSU MICROELECTRONICS LIMITED D64001S c 4 6 58 00 0 22 0 55 009 022 2 283 17 00 0 25 669 010 3 30 0 20 0 30 130 012 008 028 008 195 0 20 0 70 4 95 016 008 0543 0 20 0 40 1 378 1 778 0700 0 47 0 10 019 004 1 00 0 50 0 039 0 020 020 007 028 0 19 0 50 0 7...

Page 31: ... 64P M06 C 2003 2008 FUJITSU MICROELECTRONICS LIMITED F64013S c 5 6 0 20 008 M 18 70 0 40 736 016 14 00 0 20 551 008 1 00 039 INDEX 0 10 004 1 19 20 32 52 64 33 51 20 00 0 20 787 008 24 70 0 40 972 016 0 42 0 08 017 003 0 17 0 06 007 002 0 8 1 20 0 20 047 008 3 00 0 35 0 20 Mounting height 118 014 008 0 25 0 15 0 20 010 006 008 Stand off Details of A part A 0 10 004 Dimensions in mm inches Note Th...

Page 32: ...M09 FPT 64P M09 C 2003 2008 FUJITSU MICROELECTRONICS LIMITED F64018S c 3 6 0 65 026 0 10 004 1 16 17 32 49 64 33 48 12 00 0 10 472 004 SQ 14 00 0 20 551 008 SQ INDEX 0 32 0 05 013 002 M 0 13 005 0 145 0 055 0057 0022 A 059 004 008 0 10 0 20 1 50 0 8 0 25 010 Mounting height 0 50 0 20 020 008 0 60 0 15 024 006 0 10 0 10 004 004 Details of A part Stand off 0 10 004 Dimensions in mm inches Note The v...

Page 33: ...OPT0 to OPT5 4 Output terminals OPT0 to OPT5 of the waveform sequencer These pins output the waveforms specified at the output data buffer register of the waveform sequencer circuit Output is generated when OPE0 to OPE5 of OPCR is enabled 31 32 39 P06 E General purpose I O ports PWI0 4 PWC 0 signal input pin 32 33 40 P07 E General purpose I O ports PWO0 PWC 0 signal output pin 33 34 to 35 41 to 42...

Page 34: ...n 1 is set in EN5 in standby mode TIN0 External clock input pin for reload timer 0 39 40 47 P16 C Port input General purpose I O ports INT6 Can be used as interrupt request input channel 6 Input is enabled when 1 is set in EN6 in standby mode TO0 Event output pin for reload timer 0 40 41 48 P17 C General purpose I O ports FRCK External clock input pin for free run timer 41 42 49 P20 F General purp...

Page 35: ... 61 4 P40 F General purpose I O ports SIN0 Serial data input pin for UART channel 0 While UART channel 0 is operating for input the input of this pin is used as required and must not be used for any other input 61 62 5 P41 F General purpose I O ports SOT0 Serial data output pin for UART channel 0 This function is enabled when UART channel 0 enables data output 62 63 6 P42 F General purpose I O por...

Page 36: ...tage must not exceed AVcc Vref is fixed to AVss 13 14 21 AVSS J Vss power input pin for analog circuits 14 15 22 P60 F Port input General purpose I O ports SIN1 Serial data input pin for UART channel 1 While UART channel 1 is operating for input the input of this pin is used as required and must not be used for any other input 15 16 23 P61 F Port input General purpose I O ports SOT1 Serial data ou...

Page 37: ...for operation mode specification Connect these pins directly to Vcc or Vss 24 49 25 50 32 57 Vss Power input Power 0 V input pin 56 57 64 Vcc Power 5 V input pin 1 FPT 64P M09 2 FPT 64P M06 3 DIP 64P M01 4 Pin names are not applicable to MB90465 series Table 1 6 1 Pin Description 5 5 Pin no Pin name I O circuit Pin status during reset Function QFP M09 1 QFP M06 2 SDIP 3 ...

Page 38: ... resistor of approximately 1MΩ B Hysteresis input Resistor approximately 50 kΩ C CMOS output Hysteresis input Selectable pull up resistor approximately 50 kΩ IOL 4 mA D CMOS output CMOS input Selectable pull up resistor approximately 50 kΩ IOL 12 mA X1 X0 N ch P ch P ch N ch Standby mode control Xout R P ch N ch R P ch Pout Pull up control Hysteresis input Nout Standby mode control P ch N ch R P c...

Page 39: ...t CMOS input IOL 4 mA I CMOS output CMOS input Analog input IOL 4 mA Table 1 7 1 I O Circuit Type 2 3 Classification Type Remarks P ch N ch R P ch Pout Pull up control CMOS input Nout Standby mode control P ch N ch Pout Hysteresis input Nout Standby mode control P ch N ch Pout CMOS input Nout Standby mode control P ch N ch Pout CMOS input Nout Analog input control Analog input P ch N ch IN ...

Page 40: ... D converter reference voltage AVR input pin with protection circuit L Hysteresis input Table 1 7 1 I O Circuit Type 3 3 Classification Type Remarks P ch N ch Analog input enable Analog input enable IN P ch N ch Pout CMOS input Nout Analog input control Analog input ...

Page 41: ...22 CHAPTER 1 OVERVIEW ...

Page 42: ...23 CHAPTER 2 NOTES ON HANDLING DEVICES This chapter describes notes on Handling Devices 2 1 Notes on Handling Devices ...

Page 43: ... is not exceeded When turning the power on or off to analog circuits be sure that the analog supply voltages AVcc and AVR and analog input voltage do not exceed the digital supply voltage Vcc Stabilize of supply voltages Even within the operation guarantee range of the Vcc supply voltage a malfunction can be caused if the supply voltage undergoes a rapid change For voltage stabilization guidelines...

Page 44: ...r other malfunction To reduce extraneous emission to prevent a malfunction of the strobe signal due to an increase in the group level and to maintain the local output current rating connect all these power supply pins to an external power supply and ground them The current source should be connected to the Vcc and Vss pins of the device with minimum impedance It is recommended that a bypass capaci...

Page 45: ...26 CHAPTER 2 NOTES ON HANDLING DEVICES ...

Page 46: ... describes memory space for the MB90460 465 series 3 1 CPU 3 2 Memory Space 3 3 Memory Maps 3 4 Addressing 3 5 Memory Location of Multi byte Data 3 6 Registers 3 7 Dedicated Registers 3 8 General purpose Registers 3 9 Prefix Codes ...

Page 47: ...F2MC 16LX CPU are shown below CPU Minimum instruction execution time 62 5 ns when the source oscillation is 4 MHz and the PLL clock is multiplied by 4 Maximum memory address space 16M bytes Access in linear or bank addressing mode Instruction set optimum for controller applications Many data types bit byte word and long word As many as 23 addressing modes Enhanced high precision arithmetic operati...

Page 48: ... between the F2 MC 16LX System and the Memory Map Programs Data EI2 OS Peripheral circuits General purpose Program area Interrupt controller ports F2 MC 16LX CPU FFFFFFH FF0000H 1 000D00H 3 000100H 0000C0H 0000B0H 000000H F2MC 16LX device Internal bus Interrupts FFC000H Vector table area External area 4 External area 4 ROM area FF bank image Data area General purpose EI2 OS descriptor area registe...

Page 49: ... is used as a general purpose register general purpose register addressing enables high speed access with short instructions Extended intelligent I O service EI2 OS descriptor area address 000100H to 00017FH This area retains the transfer modes I O addresses transfer count and buffer addresses Since this area is allocated to a part of the RAM area it can be used as ordinary RAM I O Area Interrupt ...

Page 50: ... areas Model Address 1 Address 2 Address 3 MB90462 FF0000H 004000H 000900H MB90467 FF0000H 004000H 000900H MB90F462 FF0000H 004000H 000900H MB90F462A FF0000H 004000H 000900H MB90F463A FE0000H 004000H 000900H MB90V460 FF0000H 004000H 002100H Peripheral area FFFFFFH Address 1 004000H Address 3 000100H 0000C0H 000000H RAM Single chip mode ROM area ROM area Address 2 010000H FC0000H with ROM mirroring...

Page 51: ...ses of the 16 low order bits in the FF bank are the same the table in ROM can be referenced without the far specification For example when 00C000H is accessed the contents of ROM at FFC000H are actually accessed The ROM area in the FF bank exceeds 48 Kbytes and all areas cannot be seen as images in the 00 bank Because ROM data from FF4000H to FFFFFFH is seen as an image at 004000H to 00FFFFH the R...

Page 52: ... bank addressing Linear Addressing and Bank Addressing In linear addressing the 16 Mbyte space is accessed as consecutive address spaces In bank addressing the 16 Mbyte space is divided into and managed as 256 64 Kbyte banks Figure 3 4 1 is an overview of linear addressing and bank addressing memory management Figure 3 4 1 Linear Addressing and Bank Addressing Memory Management Linear addressing B...

Page 53: ...igure 3 4 2 Example of Direct Specification of a 24 bit Physical Address in Linear Addressing Addressing by Indirect Specification with a 32 bit Figure 3 4 3 Example of Indirect Specification with a 32 bit General purpose Register in Linear Addressing 17 452D 12 3456 Old program counter program New program counter program 17452DH 123456H JMPP 123456H Next instruction JMPP 123456H XXXX 003A 090700H...

Page 54: ...3 4 1 Access Space and Main Function of Each Bank Register Bank register name Access space Main function Initial value after a reset Program bank register PCB Program PC space Instruction codes vector tables and immediate value data are stored FFH Data bank register DTB Data DT space Read write data is stored Internal or external peripheral control registers and data registers are accessed 00H Use...

Page 55: ...s to the specified prefix code to be accessed See 3 9 Prefix Codes for details about prefix codes Program space Additional space Data space User stack space System stack space PCB Program Bank Register ADB Additional Bank Register USB User Stack Bank Register DTB Data Bank Register SSB System Stack Bank Register 07H 0BH 0DH FFH FFFFFFH FF0000H 0FFFFFH 0F0000H 0DFFFFH 0D0000H 0BFFFFH 0B0000H 7FFFFF...

Page 56: ...M Figure 3 5 1 shows the data configuration of multi byte data in memory The lower 8 bits of the data is located at address n and subsequent data is located at address n 1 address n 2 address n 3 and so on in this sequence Figure 3 5 1 Storage of Multi byte Data in RAM Storage of Multi byte Operand Figure 3 5 2 shows the configuration of a multi byte operand in memory Figure 3 5 2 Storage of a Mul...

Page 57: ...hat accesses multi byte data the address following FFFFH is 0000H in the same bank Figure 3 5 4 shows an example of executing an instruction that accesses multi byte data on a bank boundary Figure 3 5 4 Multi byte Data Access on a Bank Boundary 6DH F0H 35H A4H H L Address n 35A4H 6DF0H PUSH RW1 RW3 PUSHW RW1 RW3 RW1 35A4H RW3 6DF0H Stack status after execution of the PUSHW instruction SP AL before...

Page 58: ...egisters general purpose registers can be accessed without addressing Just like ordinary memory the user can specify how the register is used Figure 3 6 1 shows the location of the dedicated registers and general purpose registers in the device Figure 3 6 1 Dedicated Registers and General purpose Registers Dedicated register Accumulator User stack pointer System stack pointer Processor status Prog...

Page 59: ... register SSB Configuration of Dedicated Registers Figure 3 7 1 shows the configuration of dedicated registers Table 3 7 1 lists the initial values of the dedicated registers Figure 3 7 1 Configuration of Dedicated Registers Accumulator A User Stack Pointer USP System Stack Pointer SSP Processor Status PS Program Counter PC Direct Page Register DPR Program Bank Register PBR Data Bank Register DBR ...

Page 60: ...pointer USP Undefined System stack pointer SSP Undefined Processor status PS Program counter PC Value in reset vector contents of FFFFDCH FFFFDDH Direct page register DPR 01H Program bank register PCB Value in reset vector contents of FFFFDEH Data bank register DTB 00H User stack bank register USB 00H System stack bank register SSB 00H Additional data bank register ADB 00H Not used x Undefined PS ...

Page 61: ...it long word 16 bit word and 8 bit byte data The 4 bit data transfer instruction MOVN is an exception The explanation of 8 bit data also applies to 4 bit data For 32 bit data processing the AH register and AL register are combined For 16 bit data and 8 bit data only the AL register is used When data of byte length or less is transferred to the AL register data becomes 16 bits long by sign extensio...

Page 62: ...An instruction that zero extends the contents at address 3000H and stores the result in the AL register A before execution A after execution XXXXH 2456H 2456H 7788H DTB B5H 77H 88H MSB LSB B53000H AH AL Memory space MOVX A 3000H An instruction that stores the contents at address 3000H in the AL register A before execution A after execution XXXXH XXXXH 8F74H 2B52H DTB A6H 8FH 74H 2BH 52H 15H 38H A6...

Page 63: ...etic operation is executed are ignored The upper 8 bits of the arithmetic operation results are all zeros Initial value of the accumulator The initial value after a reset is undefined A before execution A after execution XXXXH 1234H 1234H 2B52H DTB A6H 8FH 74H 2BH 52H 15H 38H MSB LSB A61540H A6153EH RW1 6 AH AL MOVW A RW1 6 Instruction that performs a word length read using the result of the RW1 c...

Page 64: ...stack a system stack and a user stack The stack address is determined as shown in Table 3 7 2 by the S flag in the processor status PS CCR Because the S flag is initialized to 1 by a reset the system stack is used as the default Ordinarily the system stack is used for interrupt routine stack operations and the user stack is used for all other types of stack operation When separation of the stack s...

Page 65: ...bank register SSB User Stack Pointer USP To use the user stack pointer USP set the S flag in the condition code register CCR of the processor status PS to 0 The upper 8 bits of the address that will be used for the stack operation are indicated by the user stack bank register USB USP F328H XXH XXH C6F326H USB C6H AL A624H SSP 1234H SSB 56H S flag 0 Before execution USP F326H A6H 24H C6F326H USB C6...

Page 66: ... The value is compared with the value of the interrupt level setting bits ICR IL0 to IL2 in the interrupt control register set for the peripheral resource interrupt request Register bank pointer RP This pointer points to the first address of the memory block register bank used as the general purpose register in the RAM area There are 32 banks for general purpose registers Values 0 to 31 are set in...

Page 67: ...s are disabled Cleared by a reset Stack flag S This flag indicates the pointer used for a stack operation When the S flag is 0 the user stack pointer USP is valid When the S flag is 1 the system stack pointer SSP is valid Set when an interrupt is accepted or when a reset occurs Sticky bit flag T Set to 1 when the data shifted out by the carry contains at least one 1 during execution of a logical r...

Page 68: ...use of an arithmetic calculation Cleared to 0 if no overflow occurs Carry flag C Set to 1 when there is an overflow from the MSB or an underflow from the LSB because of an arithmetic calculation Cleared to 0 when there is no overflow or underflow because of an arithmetic calculation ...

Page 69: ...d the address in internal RAM where the general purpose register exists Figure 3 7 11 shows the conversion rules used for the relationship between the contents of the RP and the real address Figure 3 7 11 Conversion Rules for Physical Address of General purpose Register Area Since the RP takes a value from 00H to 1FH the first address of the register bank can be set in the range from 000180H to 00...

Page 70: ...ses the instruction only when the value interrupt level of the interrupt request is smaller than the value indicated by these bits When an interrupt is accepted the interrupt level value is set in the interrupt level mask register ILM Thereafter interrupts with the same or lower level are not accepted The interrupt level is set to the highest level which is the interrupts disabled status because t...

Page 71: ...d by the CPU is stored The PC specifies the lower 16 bits Before being used the actual address is combined to become 24 bits as shown in Figure 3 7 13 The contents of the PC are updated by conditional branch instructions subroutine call instructions interrupts and resets The PC can be used as a bus pointer for reading operands Figure 3 7 13 Program Counter PC Note The PC and PCB cannot be rewritte...

Page 72: ...g The DPR is initialized to 01H by a reset The DPR can be read and written using an instruction Figure 3 7 14 Physical Address Generation by the Direct Page Register DPR Figure 3 7 15 shows an example of direct page register DPR setting and data access Figure 3 7 15 Example of Direct Page Register DPR Setting and Data Access DTB register DDR register Direct address in instruction αααααααα ββββββββ...

Page 73: ...e 16 megabyte space are executed or when a hardware interrupt or exception occurs Data bank register DTB The DTB is a bank register that specifies the data DT space User stack bank register USB system stack bank register SSB The USB and SSB are bank registers that specify the stack SP space Whether the USB or the SSB is used depends on the S flag value in the processor status PS CCR See 3 7 2 Stac...

Page 74: ...gister All general purpose registers exist in RAM at 000180H to 00037FH and are configured as 32 banks The register bank pointer RP specifies the bank that is to be used for a general purpose register The RP points to the bank currently being used The RP determines the first address of each bank with the following formula Address of first general purpose register 000180H RP x 10H Figure 3 8 1 show...

Page 75: ... by a reset The status before a reset is retained At power on however the contents are undefined Table 3 8 1lists the typical functions of general purpose registers Table 3 8 1 Typical Functions of General purpose Registers Register name Function R0 to R7 Used as an operand in various instructions Note R0 is also used as a barrel shift counter and an instruction normalization counter RW0 to RW7 Us...

Page 76: ... to select the memory space to be accessed by the instruction regardless of the addressing method Common register bank prefix CMR The common register bank prefix is placed before an instruction that accesses a register bank to change the register accessed by the instruction to the common bank register bank selected when RP 0 at 000180H to 00018FH regardless of the current register bank pointer RP ...

Page 77: ...elect prefix Selected space PCB Program space DTB Data space ADB Additional space SPB When the value of the S flag in the condition code register CCR is 0 and the user stack space is 1 the system stack space is used Table 3 9 2 Instructions not affected by Bank Select Prefix Codes Instruction type Instruction Effect of bank select prefix String instruction MOVS MOVSW SCEQ SCWEQ FIL SFILSW The bank...

Page 78: ...pe Instruction Explanation Flag change instruction AND CCR imm8 OR CCR imm8 The effect of the prefix extends to the next instruction ILM setting instruction MOV ILM imm8 The effect of the prefix extends to the next instruction PS return instruction POPW PS Do not place a bank select prefix before the PS return instruction ...

Page 79: ...f the common register bank prefix CMR is placed before an instruction that accesses a register bank registers accessed by the instruction can be changed to the common bank register bank selected when RP 0 at 000180H to 00018FH regardless of the current register bank pointer RP value Note that caution is required when this prefix is used with the instructions listed in Table 3 9 4 Table 3 9 4 Instr...

Page 80: ...ng instruction MOVS MOVSW SCEQ SCWEQ FILS FILSW Do not place the NCC prefix before the string instruction Flag change instruction AND CCR imm8 OR CCR imm8 The condition code register CCR changes as defined in the instruction specification whether or not a prefix is used The effect of prefix extends to the next instruction PS return instruction POPW PS The condition code register CCR changes as def...

Page 81: ...upt hold suppression As shown in Figure 3 9 1 an interrupt or hold request generated during the execution of prefix codes and interrupt hold instructions is not accepted The interrupt hold is not processed until the first instruction that is not governed by a prefix code or that is not an interrupt hold suppression instruction is executed Figure 3 9 1 Interrupt hold Suppression Table 3 9 6 Prefix ...

Page 82: ...ion Figure 3 9 2 Interrupt hold Suppression Instructions and Prefix Codes Consecutive Prefix Codes As shown in Figure 3 9 3 when consecutive conflicting prefix codes PCB ADB DTB and SPB are specified the last prefix code is valid Figure 3 9 3 Consecutive Prefix Codes ADD A 01H MOV ILM imm8 MOV A FFH CCR is not changed due to NCC prefix NCC CCR XXX10XXB CCR XXX10XXB Interrupt suppression instructio...

Page 83: ...64 CHAPTER 3 CPU ...

Page 84: ...r describes the reset for the MB90460 465 series microcontrollers 4 1 Reset 4 2 Reset Causes and Oscillation Stabilization Wait Intervals 4 3 External Reset Pin 4 4 Reset Operation 4 5 Reset Cause Bits 4 6 Status of Pins in a Reset ...

Page 85: ...rence For external reset requests via the RSTX pin if the reset cause is generated during a write operation during the execution of a transfer instruction such as MOV the CPU waits for the reset to be cleared after the instruction is completed The normal write operation is therefore completed even though a reset is input concurrently Note however that waiting for the reset to be cleared may start ...

Page 86: ...mer control register WDTC within a given time after the watchdog timer is activated The oscillation stabilization wait interval can be set by the clock selection register CKSCR Power on reset A power on reset is generated when the power is turned on The oscillation stabilization wait interval is fixed at 218 oscillation clock cycles 218 HCLK After the oscillation stabilization wait interval has el...

Page 87: ... Wait Interval Oscillation Stabilization Wait and Reset State A reset operation in response to a power on reset and other externally activated resets during stop mode and hardware standby mode is performed after the oscillation stabilization wait interval has elapsed This time interval is generated by the time base timer If the external reset has not been cleared after the interval the reset opera...

Page 88: ...External Reset Pin Block diagram of internal reset Figure 4 3 1 Block Diagram of Internal Reset Note Inputs to the RSTX pin are accepted during cycles in which memory is not affected to prevent memory from being destroyed by a reset during a write operation A clock is required to initialize the internal circuit In particular an operation with an external clock requires clock input together with re...

Page 89: ... CHAPTER 4 RESET Block diagram of internal reset for external pin Figure 4 3 2 Block Diagram of Internal Reset for External Pin RSTX P ch N ch Input buffer HCLK Oscillation clock Internal reset signal Pin ...

Page 90: ... 4 1 shows the reset operation flow Figure 4 4 1 Reset Operation Flow Mode Pins Setting the mode pins MD0 to MD2 specifies how to fetch the reset vector and the mode data Fetching the reset vector and the mode data is performed in the reset sequence See 8 1 Mode Setting for details about mode pins Power on reset Stop mode reset Watchdog timer reset Oscillation stabilization wait and reset state Ex...

Page 91: ... by the setting of the mode pins If external vector mode is specified by the mode pin settings the CPU will always read the reset vector and the mode data from external memory instead of from internal ROM If single chip mode and internal ROM external bus mode are used setting the mode pins to specify internal vector mode is recommended Mode data address FFFFDFH Only the reset operation changes the...

Page 92: ...he reset has been cleared the value read from the WDTC should be processed by the software and a branch made to the appropriate program Figure 4 5 1 Block Diagram of Reset Cause Bits F F F F F F F F RSTX L S S S S R R R R Q Q Q Q Pin Without periodic clear RST bit set Power on Power on External reset Watchdog timer LPMCR RST bit Delay WDTC register WDTC register read F2MC 16LX internal bus circuit...

Page 93: ... are set to 1 Power on reset For a power on reset the PONR bit is set to 1 but all other reset cause bits are undefined Consequently program the software so that it will ignore all reset cause bits except the PONR bit if it is 1 Clearing the reset cause bits The reset cause bits are cleared only when the watchdog timer control register WDTC is read Any bit that corresponds to a reset cause that ha...

Page 94: ...mode data is read from the internal ROM Status of Pins after Mode Data is read The status of pins after mode data has been read depends on the mode data M1 and M0 00B When single chip mode has been selected M1 M0 00B All I O pins resource pins are high impedance and mode data is read from the internal ROM Note For those pins that change to high impedance when a reset cause is generated take care t...

Page 95: ...76 CHAPTER 4 RESET ...

Page 96: ...B90460 465 series microcontrollers 5 1 Clock 5 2 Block Diagram of the Clock Generation Block 5 3 Clock Selection Register CKSCR 5 4 Clock Mode 5 5 Oscillation Stabilization Wait Interval 5 6 Connection of an Oscillator or an External Clock to the Microcontroller ...

Page 97: ...l oscillator attached to the oscillation circuit or by input of an external clock Main clock MCLK The main clock which is the oscillation clock divided by 2 supplies the clock input to the time base timer and the clock selector PLL clock PCLK The PLL clock is obtained by multiplying the oscillation clock with the internal PLL clock multiplier circuit PLL oscillation circuit Selection can be made f...

Page 98: ...ock Supply Map Watchdog timer Peripheral function X0 X1 HCLK MCLK PCLK PPG2 1 2 3 4 TO0 UART0 PLL multiplier circuit Clock selecter Clock generation block Divide by 2 UART1 CPU Machine clock SCK0 SIN0 SOT1 16 bit free run timer Pin Pin Pin Pin Pin Pin Pin Pin PPG0 PPG1 16 bit PPG timer 0 16 bit PPG timer 1 16 bit reload timer 0 System clock generation circuit Time base timer Oscillation stabilizat...

Page 99: ...MD RESV WS0 MCM MCS CS1 CS0 WS1 RESV 3 2 Low power mode control register LPMCR Pin Pin Pin Divide by 2 Divide by 512 Divide by 2 Divide by 4 Divide by 4 PLL multipiler circuit System clock generation circuit Time base timer Stop signal Release reset Cancel interrupt CPU clock Pin Hi z control Clock selector Clock selection register CKSCR Stop and sleep signals Machine clock Main clock Oscillation ...

Page 100: ...clocks the clock selector selects the clock that is supplied to the CPU and peripheral clock control circuits Clock selection register CKSCR The clock selection register is used to set switching between the oscillation clock and a PLL clock selection of an oscillation stabilization wait interval and selection of a PLL clock multiplier Oscillation stabilization wait interval selector This selector ...

Page 101: ... resulting clock frequency is shown in parentheses Oscillation stabilization wait interval selection bits The corresponding time interval for an oscillation clock frequency of 4 MHz is given in parentheses Machine clock selection bit 0 0 1 1 0 1 0 1 1 x HCLK 4MHz 2 x HCLK 8MHz 3 x HCLK 12MHz 4 x HCLK 16MHz 2 10 HCLK Approx 0 256ms 2 13 HCLK Approx 2 05ms 215 HCLK Approx 8 19ms 2 17 HCLK Approx 32 ...

Page 102: ...hen this bit is 1 the main clock is selected If this bit has been set to 1 and 0 is written to it the oscillation stabilization wait interval for the PLL clock starts As a result the time base timer is auto matically cleared and the TBOF bit of the time base timer control register TBTC is also cleared For PLL clocks the oscillation stabilization period is fixed at 214 HCLK the oscillation stabiliz...

Page 103: ...d 1 is written to it the switch from the PLL clock to the main clock occurs when the edges of the PLL clock and the main clock coincide after 1 to 8 PLL clocks Note Even though the MCS bit of CKSCR is rewritten machine clock switching does not occur immediately When operating a resource that depends on the machine clock make sure that machine clock switching has been done by referring to the MCM b...

Page 104: ...0 CS1 CS0 11 PLL2 Main MCS 1 MCM 0 CS1 CS0 01 PLL3 Main MCS 1 MCM 0 CS1 CS0 11 PLL4 Main MCS 1 MCM 0 CS1 CS0 11 1 2 3 4 5 6 7 7 7 7 6 6 6 6 Machine clock selection bit of CKSCR Machine clock indication bit of CKSCR Multiplier selection bits of CKSCR 1 The MCS bit is cleared 2 The PLL clock oscillation stabilization wait ends with CS1 and CS0 00 3 The PLL clock oscillation stabilization wait ends w...

Page 105: ...ion starts and is allowed only after full stabilization of oscillation After the oscillation stabilization wait interval has elapsed the clock is supplied to the CPU Because the oscillation stabilization time depends on the type of the oscillator crystal ceramic etc the proper oscillation stabilization wait interval for the oscillator used must be selected An oscillation stabilization wait interva...

Page 106: ... External Clock to the Microcontroller Example of connecting a crystal or ceramic oscillator to the microcontroller Connect a crystal or ceramic oscillator as shown in the example in Figure 5 6 1 Figure 5 6 1 Example of Connecting a Crystal or Ceramic Oscillator to the Microcontroller Example of connecting an external clock to the microcontroller As shown in Figure 5 6 2 connect an external clock ...

Page 107: ...88 CHAPTER 5 CLOCK ...

Page 108: ...llers 6 1 Low Power Consumption Mode 6 2 Block Diagram of the Low Power Consumption Control Circuit 6 3 Low Power Consumption Mode Control Register LPMCR 6 4 CPU Intermittent Operation Mode 6 5 Standby Mode 6 6 State Change Diagram 6 7 State of Pins in Standby Mode and during Reset 6 8 Usage Notes on Low Power Consumption Mode ...

Page 109: ...ows the relation between the CPU operating modes and current consumption Figure 6 1 1 CPU Operating Modes and Current Consumption Current consumption Several tens CPU operating of mA mode PLL clock mode Multiplied by four clock Multiplied by three clock Multiplied by two clock Multiplied by 1 clock Multiplied by four clock Multiplied by three clock Multiplied by two clock Multiplied by 1 clock PLL...

Page 110: ... oscillation clock itself stop mode reducing power consumption PLL sleep mode PLL sleep mode is activated to stop the CPU operating clock when the microcontroller enters PLL clock mode other components continue to operate on the PLL clock Main sleep mode Main sleep mode is activated to stop the CPU operating clock when the microcontroller enters main clock mode other components continue to operate...

Page 111: ...ontrol circuit X0 2 X1 RSTX RST STP RST SLP CG1 CG0 RESV SPL TMD RESV WS0 MCM MCS CS1 CS0 WS1 RESV 3 2 Low power mode control register LPMCR Pin Pin Pin Divide by 2 Divide by 512 Divide by 2 Divide by 4 Divide by 4 PLL multipiler circuit System clock generation circuit Time base timer Stop signal Release reset Cancel interrupt CPU clock Pin Hi z control Clock selector Clock selection register CKSC...

Page 112: ...supplied to peripheral functions for the peripheral clock control Peripheral clock control circuit This circuit controls the clocks supplied to peripheral functions Pin high impedance control circuit This circuit makes the external pins high impedance when the microcontroller enters time base timer mode and stop mode For the pins with the pull up option this circuit disconnects the pull up resisto...

Page 113: ...ipheral clock 9 clock pulses CPU clock Peripheral clock 1 3 to 4 approx 17 clock pulses CPU clock Peripheral clock 1 5 to 6 approx 33 clock pulses CPU clock Peripheral clock 1 9 to 10 approx 0 1 1 0 1 1 CG0 CPU halt clock pulses selection bits RST 0 Generates an internal reset signal of 3 machine cycles No change no effect on operation 1 Internal reset signal generation bit SPL 0 Retained High imp...

Page 114: ...e is in effect When this bit is 0 the level of the external pins is retained When this bit is 1 the status of the external pins changes to high impedance This bit is initialized to 0 by a reset bit4 RST Internal reset signal generation bit When 0 is written to this bit an internal reset signal of 3 machine cycles is generated Writing 1 to this bit has no effect on operation The read value of this ...

Page 115: ...ns not listed in Table 6 3 2 any instruction can be used When word length is used for writing to the low power consumption mode control register even addresses must be used Writing with odd addresses to switch to low power consumption mode may cause a malfunction Table 6 3 2 Instructions to be used for switching to Low Power Consumption Mode MOV io imm8 MOV io A MOV RLi disp8 A MOVW io imm16 MOVW ...

Page 116: ...uced enabling processing with low power consumption The CG1 and CG0 bits of the low power consumption mode control register LPMCR are used to select the number of clock pulses per halt cycle of the clock supplied to the CPU External bus operation uses the same clock as that used for peripheral functions Instruction execution time in CPU intermittent mode can be calculated A correction value should...

Page 117: ...Active Active Reset or Interrupt Main sleep mode MCS 1 SLP 1 Time base timer mode PLL time base timer mode SPL 0 MCS 0 TMDX 0 Inactive Hold PLL time base timer mode SPL 1 Hi Z Main time base timer mode SPL 0 MCS 1 STP 1 Hold Main time base timer mode SPL 1 Hi Z Stop mode Main PLLstop mode SPL 0 MCS x STP 1 Inactive Inactive Inactive Hold Main PLLstop mode SPL 1 Hi Z Only the time base timer is act...

Page 118: ...0 to TMDX bit at the same time the mode switches to stop time base timer mode Data retention function In sleep mode the contents of dedicated registers such as accumulators and internal RAM are retained Operation during an interrupt request Writing 1 to the SLP bit of LPMCR during an interrupt request does not trigger a switch to sleep mode If the CPU does not accept the interrupt the CPU executes...

Page 119: ...Sleep Mode for an Interrupt Note When interrupt processing is executed normally the CPU first executes the instruction that follows the instruction in which switching to sleep mode was specified The CPU then proceeds to interrupt processing Return to normal mode from PLL sleep mode by an external reset During PLL sleep mode the main clock and the PLL clock generate clock pulses Since an external r...

Page 120: ...TION MODE Figure 6 5 2 Release of PLL Sleep Mode by External Reset RSTX pin Sleep mode Main clock PLL clock CPU clock CPU operation Sleep mode released Inactive Oscillating PLL clock Reset sequence Execution Reset cleared Oscillating ...

Page 121: ...interrupt request does not trigger switching to time base timer mode Status of pins Selection of whether the external pins retain the state they had immediately before switching to time base timer mode or go to high impedance with switching to this mode can be controlled by the SPL bit of LPMCR Release of Time base Timer Mode The low power consumption control circuit releases time base timer mode ...

Page 122: ... CPU executes processing according to the settings of the I flag of the condition code register CCR interrupt level mask register ILM and interrupt control register ICR If the interrupt is accepted the CPU executes interrupt processing If the interrupt is not accepted the CPU resumes execution with the instruction that follows the instruction in which switching to time base timer mode was specifie...

Page 123: ...mal mode from stop mode the low power consumption control circuit puts the microcontroller into the oscillation stabilization wait state then releases stop mode Return to normal mode by a reset When stop mode is released by a reset cause the microcontroller is placed in the oscillation stabilization wait and reset state after release from stop mode The reset sequence proceeds after the oscillation...

Page 124: ...CPU then proceeds to interrupt processing Figure 6 5 4 shows the operation of return to normal mode from stop mode Figure 6 5 4 Release of Main Stop Mode by External Reset RSTX pin Stop mode Main clock Inactive CPU clock CPU operation Stop mode released Reset cleared Oscillation stabilization wait time Oscillating Oscillating Main PLL clock PLL clock Oscillation stabilization wait time Reset seque...

Page 125: ... register CKSCR If the mode is switched to another clock mode or low power consumption mode before completion of switching the mode may not be switched Source Osc stabilization wait and reset state Main clock reset state Power on Main run state Main sleep state Main Stop state Source clock osc stabilization wait state 9 8 7 10 5 2 3 4 21 22 Main clock mode Main time base timer state 6 11 PLL stop ...

Page 126: ...nterrupt Main PLL stop SPL 0 MCS x STP 1 Inactive Inactive Inactive Inactive Hold Reset or interrupt Main PLL stop SPL 1 MCS x STP 1 Inactive Inactive Inactive Inactive Hi Z Reset or interrupt Table 6 6 2 Clock Mode Wwitching and Release Transition Conditions After power on transition to the main run state 1 Source clock oscillation stabilization wait interval ends Time base timer output 2 Reset i...

Page 127: ...e Release of PLL stop mode 14 Interrupt input 15 indicates return to PLL run state after oscillation stabilization wait 16 External reset 18 indicates external reset during oscillation stabilization wait state Transition to PLL sleep mode 1 SLP 1 MCS 0 Transition from PLL run state 2 SLP 1 MCS 0 Transition from main run state switch to PLL clock after PLL clock oscillation stabilization wait Relea...

Page 128: ...nput function is enabled when corresponding external interrupt pin is enable Select either the pull up or the pull down option Alternatively an external input is required Pins used as output ports are the same as other ports 2 The preceding state is retained means that the state of the pin output existing immediately before switching to this mode is retained Note that input is disabled if the prec...

Page 129: ...sed This action does not depend on whether the CPU accepts that interrupt After the release of standby mode normal interrupt processing is performed The CPU branches to the interrupt handling routine provided that the priority of the interrupt request indicated by the interrupt level setting bits IL2 IL1 and IL0 of ICR is higher than the interrupt level mask register ILM and the interrupt enable f...

Page 130: ...used as the oscillation stabilization wait interval PLL clock oscillation stabilization wait interval The CPU may be working with the main clock and the PLL clock may be stopped If the microcontroller will enter a mode in which the CPU and peripheral functions work with the PLL clock the PLL clock initially enters the oscillation stabilization wait state In this state the CPU still operates using ...

Page 131: ...112 CHAPTER 6 LOW POWER CONSUMPTION MODE ...

Page 132: ...nterrupt 7 2 Interrupt Causes and Interrupt Vectors 7 3 Interrupt Control Registers and Peripheral Functions 7 4 Hardware Interrupt 7 5 Software Interrupt 7 6 Interrupt of Extended Intelligent I O Service EI2OS 7 7 Exception Processing Interrupt 7 8 Stack Operations for Interrupt Processing 7 9 Sample Programs for Interrupt Processing ...

Page 133: ...rrupt instruction such as the INT instruction Interrupt from extended intelligent I O service EI2 OS The EI2 OS function automatically transfers data between a peripheral function and memory Data transfer which has ordinarily been executed by an interrupt processing program can be handled like a direct memory access DMA When the specified number of data transfers has been terminated the interrupt ...

Page 134: ...ing type instruction is being executed the interrupt is evaluated in each step Interrupt activation return processing EI OS processing EI2 OS Software Hardware Return interrupt exception processing Interrupt processing EI2 OS Save the dedicated Disable acceptance of register on the system stack hardware interrupts I 0 Save the dedicated register on the system stack Return the dedicated register fr...

Page 135: ...EI2 OS exception processing hardware and software interrupt Table 7 2 1 shows the assignment of interrupt numbers and interrupt vectors Table 7 2 1 Interrupt Vectors Software interrupt instruction Vector address L Vector address M Vector address H Mode data Interrupt no Hardware interrupt INT0 FFFFFCH FFFFFDH FFFFFEH Not used 0 None INT7 FFFFE0H FFFFE1H FFFFE2H Not used 7 None INT8 FFFFDCH FFFFDDH...

Page 136: ... 0 1 detection O 20 14H FFFFACH DTTI0 Output compare channel 4 match O 21 15H FFFFA8H ICR05 0000B5H 1 DTP ext interrupt channels 2 3 detection O 22 16H FFFFA4H DTTI1 Output compare channel 5 match O 23 17H FFFFA0H ICR06 0000B6H 1 End of measurement by PWC1 timer PWC1 timer over flow O 24 18H FFFF9CH DTP ext interrupt channels 4 5 detection O 25 19H FFFF98H ICR07 0000B7H 1 Waveform sequencer timer ...

Page 137: ...he service can be started by either of the function And if EI2 OS clear is supported both interrupt request flags for the two interrupt causes are cleared by EI2 OS interrupt clear signal It is recommended to mask either of the interrupt request during the use of EI2OS EI2 OS service cannot be started multiple times simultaneously Interrupt other than the operating interrupt is masked during EI2 O...

Page 138: ...r 1 0000B4H Interrupt control register 04 ICR04 Output compare 3 DTP external interrupt 0 1 DTTI0 0000B5H Interrupt control register 05 ICR05 Output compare 4 DTP external interrupt 2 3 DTTI1 0000B6H Interrupt control register 06 ICR06 Output compare 5 PWC timer 1 0000B7H Interrupt control register 07 ICR07 DTP external interrupt 4 5 waveform sequencer 0000B8H Interrupt control register 08 ICR08 D...

Page 139: ... as interrupt of the corresponding peripheral function Select an extended intelligent I O service EI2 OS channel Display the status of the extended intelligent I O service EI2 OS Some of the functions of the interrupt control registers ICR differ during writing and reading as shown in Figure 7 3 1 and Figure 7 3 2 Note Do not use a read modify write instruction to access the interrupt control regi...

Page 140: ... 0 0 0 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 1 IL1 IL0 Interrupt level setting bit Interrupt level 0 highest Interrupt level 7 no interrupt ISE 0 1 EI2OS enable bit Activates the interrupt sequence when an interrupt occurs Activates EI2OS when an interrupt occurs ICS3 ICS2 ICS1 ICS0 Channel 0 0 0 0 0 000100H 1 000108H 2 000110H 3 000118H 4 000120H 5 000128H 6 000130H 7 000138H 8 000140H 9 000148H 10...

Page 141: ...highest Interrupt level 7 no interrupt ISE 0 1 EI2OS enable bit Activates the interrupt sequence when an interrupt occurs Activates EI2OS when an interrupt occurs S1 S0 0 0 0 1 1 0 1 1 EI2OS status EI2OS operation in progress or EI2OS not activated Stopped status due to count termination Reserved Stopped status due to a request from the peripheral function S1 7 bit Reading R R R W R W R W R W 6 5 ...

Page 142: ... valid only when the extended intelligent I O service EI2 OS has been activated To activate EI2OS set the ISE bit to 1 To not activate EI2OS set the ISE bit to 0 When EI2 OS is not activated setting ICS3 to ICS0 is optional ICS1 and ICS0 are valid only for writing S1 and S0 are valid only for reading Interrupt Control Register Functions Interrupt level setting bits IL2 to IL0 These bits set the in...

Page 143: ...S0 These write only bits specify the EI2 OS channel The EI2 OS descriptor address is determined based on the value set here The ICS bit is initialized to 0000B by a reset Table 7 3 3 shows the correspondence between the EI2OS channel selection bits and descriptor addresses Table 7 3 2 Correspondence between the Interrupt Level Setting Bits and Interrupt Levels IL2 IL1 IL0 Interrupt level 0 0 0 0 h...

Page 144: ...0140H 1 0 0 1 9 000148H 1 0 1 0 10 000150H 1 0 1 1 11 000158H 1 1 0 0 12 000160H 1 1 0 1 13 000168H 1 1 1 0 14 000170H 1 1 1 1 15 000178H Table 7 3 3 Correspondence between the EI2OS Channel Selection Bits and Eescriptor Addresses 2 2 ICS3 ICS2 ICS1 ICS0 Selected channel Descriptor address Table 7 3 4 Relationship between EI2OS Status Bits and the EI2OS Status S1 S0 EI2 OS status 0 0 EI2 OS operat...

Page 145: ...e automatically saved on the system stack The currently requested interrupt level is stored in the interrupt level mask register ILM and the function branches to the corresponding interrupt vector Multiple interrupts Multiple hardware interrupts can be activated Extended intelligent I O service EI2 OS EI2 OS is an automatic transfer function between memory and I O When the specified transfer count...

Page 146: ...rea allocated to the control register of the peripheral function control register and data register Figure 7 4 1 shows hardware interrupt operation during writing to the built in resource area Figure 7 4 1 Hardware Interrupt Request while writing to the Peripheral Function Control Register Area Table 7 4 1 Mechanisms used for Hardware Interrupt Mechanism Function Peripheral function Interrupt enab...

Page 147: ...rrupt is not processed until the first time an instruction of a different type is executed Hardware interrupt suppression during execution of software interrupt When a software interrupt is activated the I flag is cleared to 0 In this state other interrupt requests cannot be accepted Table 7 4 2 Hardware Interrupt Suppression Instruction Prefix code Interrupt hold suppression instructions instruct...

Page 148: ...ived interrupt level ICR IL2 to IL0 and the interrupt level mask register ILM If IL ILM and interrupts are enabled PS CCR I 1 the CPU activates the interrupt processing microcode after the instruction currently being executed terminates At the beginning of the interrupt processing microcode the CPU references the ISE bit in the interrupt control register ICR If ISE 0 the CPU continues the executio...

Page 149: ... If the comparison indicates a higher priority than the current interrupt processing level the CPU checks the contents of the I flag in the condition code register CCR 6 If in the check in 5 the I flag is interrupt enabled I 1 the CPU waits until the execution of the instruction currently being executed terminates At termination the CPU sets the requested level IL in the ILM 7 Registers are saved ...

Page 150: ...nated Alter natively is there a termination request from the peripheral function Fetch the next instruction and deode Execute ordinary instruction including interrupt processing Repetition of string type instruction completed Move the pointer to the next instruction by PC update Return the dedicated registers from the system stack call the interrupt routine and return to the previous routine I 0 D...

Page 151: ... the peripheral function causes a hardware interrupt request 7 The interrupt processing hardware saves the registers and branches to the interrupt processing program 8 The interrupt processing program processes the peripheral function in response to the generated interrupt 9 Clear the peripheral function interrupt request 10 Execute the interrupt return instruction and return to the program before...

Page 152: ...t processing if an interrupt request with the same or lower priority interrupt level is generated the new interrupt request is held until the current interrupt terminates unless the I flag or ILM is changed Other multiple interrupts to be activated during an interrupt can be temporarily disabled by setting the I flag in the condition code register CCR in the interrupt processing routine to interru...

Page 153: ...inated When the interrupt processing terminates and the return instruction RETI is executed the values of the dedicated registers A DPR ADB DTB PCB PC and PS are returned from the stack and the interrupt level mask register ILM has the value that it had before the interrupt Main program A D interrupt processing Timer interrupt processing Peripheral initialization A D interrupt generated Main proce...

Page 154: ...e The interrupt request sampling wait time is the time from the generation of and interrupt request to the termination of the instruction currently being executed Whether an interrupt request has been generated is determined by sampling the instruction for an interrupt request in the final cycle of the instruction Consequently the CPU cannot identify an interrupt request during execution of each i...

Page 155: ...s returned from an interrupt θ 11 6 Z machine cycles RETI instruction The interrupt handling time is different for each address pointed to by the stack pointer Table 7 4 3 shows the interpolation values Z for the interrupt handling time Reference One machine cycle corresponds to one clock cycle of the machine clock φ Table 7 4 3 Interpolation Values Z for the Interrupt Handling Time Address pointe...

Page 156: ...he INT instruction the I flag of the condition code register CCR is set to 0 and hardware interrupts are masked To enable hardware interrupts during software interrupt processing set the I flag to 1 in the software interrupt processing routine Software interrupt operation When the CPU fetches the INT instruction the software interrupt processing microcode is activated This microcode saves the inte...

Page 157: ...cessing is performed Branch processing is then executed 3 The RETI instruction in the user interrupt processing routine terminates the interrupt processing Note When the program bank register PCB is FFH the vector area of the CALLV instruction overlaps the INT vct8 instruction table When creating the software be careful of the duplicated address of the CALLV instruction and INT vct8 instruction RA...

Page 158: ... Because transfer can be stopped depending on the peripheral function I O status unnecessary data transfer can be eliminated Incrementing or no update can be selected for the buffer address Incrementing or no update can be selected for the I O register address Extended intelligent I O service EI2 OS termination interrupt When data transfer by EI2 OS terminates a termination condition is set in the...

Page 159: ...oller selects the descriptor 3 The transfer source and transfer destination are read from the descriptor 4 Transfer is performed between I O and memory 5 The interrupt cause is automatically cleared by by BAP by IOA ISD by ICS CPU Memory space I O register Buffer Peripheral Interrupt request 1 Interrupt control register ICR Interrupt controller I O register DCT function I O 5 2 3 3 4 ISD IOA BAP I...

Page 160: ... ISD Registers of the extended intelligent I O service EI2 OS descriptor ISD High order 8 bits of data counter DCTH Low order 8 bits of data counter DCTL High order 8 bits of I O address pointer IOAH Low order 8 bits of I O address pointer IOAL EI2 OS status register ISCS High order 8 bits of buffer address pointer BAPH Medium order 8 bits of buffer address pointer BAPM Low order 8 bits of buffer ...

Page 161: ...ster that indicates the lower address A15 to A00 of the I O register used to transfer data to and from the buffer The upper address A23 to A16 is all zeros Any I O from 000000H to 00FFFFH can be specified by address Figure 7 6 4 shows the configuration of the IOA Figure 7 6 4 Configuration of I O Register Address Pointer IOA B15 B14 B13 B12 B11 B10 B09 B08 15 14 13 12 11 10 9 8 DCTH X X X X X X X ...

Page 162: ...f the BAP change the upper 8 bits BAPH do not change Figure 7 6 6 shows the configuration of the BAP Initial value EI2 OS termination control bit Not terminated by a request from the peripheral function Terminated by a request from the peripheral function Data transfer direction specification bit I O register address pointer buffer address pointer Buffer address pointer I O register address pointe...

Page 163: ...ress pointer IOA extends from 000000H to 00FFFFH The area that can be specified with the buffer address pointer BAP extends from 000000H to FFFFFFH The maximum transfer count that can be specified by the data counter DCT is 65 536 64 Kbytes Initial value xxxxxxB BAPH BAPM BAPL R W R W R W BAP 23 16 15 8 7 0 R W Read write x Undefined bit ...

Page 164: ...ecrement DCT NO NO NO NO NO NO NO YES YES YES YES 1 YES Updage value by BW Updage value by BW YES EI2OS termination processing YES Set S1 and S0 to 00 Set S1 and S0 to 01 Clear ISE to 0 Interrupt sequence Clear interrupt request from the peripheral function Return to CPU operation Set S1 and S0 to 11 Interrupt sequence Data indicated by BAP data transfer memory indicated by IOA Update IOA Update B...

Page 165: ...ware processing Hardware processing Set the system stack area Set the EI2 OS descriptor Initialize the peripheral function Set the interrupt control register ICR Set the built in resource to start operation Set the interrupt enable bit Set the ILM and I in the PS Execute the user program Transfer data Branch to interrupt vector S1 S0 01 or S1 S0 11 Decide whether to end counting or to branch to an...

Page 166: ...ster ISCS setting Unit Machine cycle One machine cycle corresponds to one clock cycle of the machine clock φ As shown in Table 7 6 3 interpolation is necessary depending on the EI2OS execution condition Table 7 6 2 Extended Intelligent I O Service Execution Time EI2 OS termination control bit SE setting Terminates due to termination request from the peripheral Ignores termination request from the ...

Page 167: ...quest from the peripheral function I O When data transfer by EI2OS is terminated before completion due to a termination request from the peripheral function I O ICR S1 S0 11B the data transfer is not performed and a hardware interrupt is activated The EI2 OS processing time is calculated with the following formula Z in the formula indicates the interpolation value for the interrupt handling time T...

Page 168: ...ent to the INT 10 software interrupt instruction is executed The following processing is executed before exception processing branches to the interrupt routine The A DPR ADB DTB PCB PC and PS registers are saved to the system stack The I flag of the condition code register CCR is cleared to 0 and hardware interrupts are masked The S flag of the condition code register CCR is set to 1 and the syste...

Page 169: ...ional data bank register ADB Data bank register DTB Program bank register PCB Program counter PC Processor status PS Figure 7 8 1 shows the stack operations at the start of interrupt processing Figure 7 8 1 Stack Operations at the Start of Interrupt Processing Stack Operations on Return from Interrupt Processing When the interrupt return instruction RETI is executed at the termination of interrupt...

Page 170: ...te the system stack area user stack area and data area so that they do not overlap System stack and user stack The system stack area is used for interrupt processing When an interrupt occurs the user stack area being used is forcibly switched to the system stack The system stack area must be set correctly even in a system that mainly uses the user stack area If division of the stack space is not p...

Page 171: ...register ICR04 EQU 0B4H Interrupt control register STACK SSEG Stack RW 100 STACK_T RW 1 STACK ENDS Main program CODE CSEG START MOV RP 0 General purpose registers use the first bank MOV ILM 07H Sets ILM in PS to level 7 MOV A STACK_T Sets system stack MOV SSB A MOVW A STACK_T Sets stack pointer then MOVW SP A Sets SSP because S flag 1 MOV DDR1 00000000B Sets P10 INT0 pin to input OR CCR 40H Sets I...

Page 172: ...gnal input to the INT0 pin and activates the extended intelligent I O service EI2OS 2 When the H level is input to the INT0 pin EI2OS is activated Data is transferred from port 0 to the memory at the 3000H address 3 The number of transfer data bytes is 100 bytes After 100 bytes are transferred an interrupt is generated because EI2OS transfer has terminated Sample coding DDR1 EQU 000011H Port 1 dir...

Page 173: ...er MOV A STACK_T Sets the system stack MOV SSB A MOVW A STACK_T Sets the stack pointer then MOVW SP A Sets SSP because the S flag 1 MOV I DDR1 00000000B Sets the P10 INT0 pin to input MOV BAPL 00H Sets the buffer address 003000H MOV BAPM 30H MOV BAPH 00H MOV ISCS 00010001B No I O address update byte transfer buffer address updated I O buffer transfer terminated by the peripheral function MOV IOAL ...

Page 174: ...s LOOP BRA LOOP Infinite loop Interrupt program WARI CLRB ER0 Clears interrupt DTP request flag User processing Checks EI2 OS termination factor processes data in buffer sets EI2OS again RETI CODE ENDS Vector processing VECT CSEG ABS 0FFH ORG 0FFACH Sets vector for interrupt 20 14H DSL WARI ORG 0FFDCH Sets reset vector DSL START DB 00H Sets single chip mode VECT ENDS END START ...

Page 175: ...156 CHAPTER 7 INTERRUPT ...

Page 176: ...157 CHAPTER 8 MODE SETTING This chapter describes the operating modes and memory access modes supported by the MB90460 465 series 8 1 Mode Setting 8 2 Mode Pins MD2 to MD0 8 3 Mode Data ...

Page 177: ... is only used in single chip mode set MD2 MD1 MD0 to 011B and set M1 M0 to 00B Bus Mode The bus mode controls the operation of internal ROM and external access functions and is specified by the mode setting pin MDx and Mx bit contents in mode data The mode setting pin MDx specifies bus mode when reset vector and mode data are read The Mx bit in mode data specifies bus mode during normal operation ...

Page 178: ... Note Because the MB90460 465 series is only used in single chip mode set MD2 MD1 MD0 to 011B and set M1 M0 to 00B Table 8 2 1 Mode Pin Settings MD2 MD1 MD0 Mode name Reset vector access area External data bus width Remarks 0 0 0 Setting not allowed 0 0 1 0 1 0 0 1 1 Internal vector mode Internal Mode data The reset sequence and subsequent sequences are controlled by mode data 1 0 0 Setting not al...

Page 179: ...e settings in the register take effect after the reset sequence Figure 8 3 1 shows the mode data configuration Figure 8 3 1 Mode Data Configuration Bus Mode Setting Bits The bus mode setting bits specify operating mode after a reset sequence Table 8 3 1 lists the relationship between the bits and functions Note Because the MB90460 465 series is only used in single chip mode set MD2 MD1 MD0 to 011B...

Page 180: ... and Mode Data Table 8 3 2 lists the relationship between mode pins and mode data Note The MB90460 465 series is only used in single chip mode FFFFFFH FF0000H 00FFFFH 000100H 0000C0H ROM ROM RAM I O Model 1 Model 2 Model 3 000000H No access Internal access Note Model x becomes the model dependent address When ROM mirroring function is selected Table 8 3 2 Relationship between Mode Pins and Mode Da...

Page 181: ...162 CHAPTER 8 MODE SETTING ...

Page 182: ... This chapter describes the functions and operation of the I O port 9 1 Overview of I O Port 9 2 Registers of I O Port 9 3 Port 0 9 4 Port 1 9 5 Port 2 9 6 Port 3 9 7 Port 4 9 8 Port 5 9 9 Port 6 9 10 Sample I O Port Program ...

Page 183: ...eral purpose I O port resource UART1 External interrupt Table 9 1 1 summarizes the functions of individual port Table 9 1 1 Functions of Individual Port Port Pin Input form Output form Function bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Port 0 P00 OPT0 to P07 PWO0 CMOS CMOS pull up resistor selectable General I O port P07 P06 P05 P04 P03 P02 P01 P00...

Page 184: ...te Port 5 is also used as analog input pins To use the port as a general purpose port be sure to reset the corresponding bit of the analog data input enable register ADER to 0 Resetting the CPU sets the ADER register bits to 1 ...

Page 185: ...r PDR2 R W 000002H XXXXXXXXB Port 3 data register PDR3 R W 000003H XXXXXXXXB Port 4 data register PDR4 R W 000004H XXXXXXXB Port 5 data register PDR5 R W 000005H XXXXXXXXB Port 6 data register PDR6 R W 000006H XXXXB Port 0 data direction register DDR0 R W 000010H 00000000B Port 1 data direction register DDR1 R W 000011H 00000000B Port 2 data direction register DDR2 R W 000012H 00000000B Port 3 dat...

Page 186: ...ster DDR0 Port 0 pull up resistor setting register RDR0 Port 0 Pins The port 0 I O pins are also used as resource I O pins Therefore the pins cannot be used as general purpose I O port pins when they are used as resource I O pins Table 9 3 1 lists the port 0 pins See 1 7 I O Circuit Types for information on the circuit types Table 9 3 1 Port 0 Pins Port Pin Port function single chip mode Resource ...

Page 187: ...to one basis Table 9 3 2 lists the port 0 pins and their corresponding register bits See 1 7 I O Circuit Types for information on the circuit types Internal data bus Port data register PDR PDR read PDR write Output latch DDR read DDR write Direction latch Port data direction register DDR Pin Standby control SPL 1 Resource output Resource output enable RDR Pull up resistor About 50k Direct resource...

Page 188: ...in is set as an input port Port 0 pull up resistor setting register RDR0 The RDR0 register specifies the selection of a pull up resistor at each pin bit of port 0 When a RDR0 register bit is 1 a pull up resistor is selected for the corresponding port pin When the bit is 0 the pull up resistor is deselected Notes When a resource having output pins is used the port functions as resource output pins ...

Page 189: ...th 1 When the pin functions as an output port the pin is set to the high level Port 0 data direction register DDR0 0 The direction latch is 0 The output buffer is turned off to place the port in input mode R W 000010H 00000000B 1 The direction latch is 1 The output buffer is turned on to place the port in output mode Port 0 pull up resistor setting register RDR0 0 The setting latch is 0 The pull u...

Page 190: ...tion in input mode Resetting a bit of the DDR0 register to 0 places the corresponding port pin in input mode In input mode the output buffer is turned off and the pins are placed in a high impedance state However when the RDR0 register is set to 1 to select a pull up resistor the pins are held at the high level Data written to the PDR0 register in input mode is held in the output latch of the PDR ...

Page 191: ...placed in a high impedance state This is because the output buffer is turned off forcibly regardless of the value in the DDR0 register Note that the inputs are fixed at a certain level to prevent leakage due to an open circuit Note also that when a pull up resistor is selected the port pins are held at the high level and not placed in a high impedance state even when the SPL bit is set to 1 Table ...

Page 192: ...also used as resource input pins The pins cannot be used as output port pins when they are used as resource input pins Table 9 4 1 lists the port 1 pins See 1 7 I O Circuit Types for information on the circuit types Table 9 4 1 Port 1 Pins Port Pin Port function Resource function I O form Circuit type Input Output Port 1 P10 INT0 DTTI0 P10 General purpose I O INT0 DTTI0 External interrupt input wa...

Page 193: ...d to the port 1 pins on a one to one basis Table 9 4 2 lists the port 1 pins and their corresponding register bits Internal data bus Port data register PDR PDR read PDR write Output latch DDR read DDR write Direction latch Port data direction register DDR Pin Standby control SPL 1 Resource output Resource output enable RDR Pull up resistor Resource input About 50k Table 9 4 2 Port 1 Pins and their...

Page 194: ... resource having input pins reset the port direction register bit corresponding to each resource input pin to 0 to place the port in input mode Table 9 4 3 lists the functions of the port 1 registers Table 9 4 3 Port 1 Register Functions Register Data During reading During writing Read Write Address Initial value Port 1 data register PDR1 0 The pin is at the low level The output latch is loaded wi...

Page 195: ...on in input mode Resetting a bit of the DDR1 register to 0 places the corresponding port pin in input mode In input mode the output buffer is turned off and the pins are placed in a high impedance state However when the RDR1 register is set to 1 to select a pull up resistor the pins are held at the high level Data written to the PDR1 register in input mode is held in the output latch of the PDR bu...

Page 196: ...he output buffer is turned off forcibly regardless of the value in the DDR1 register Note that the inputs are fixed at a certain level to prevent leakage due to an open circuit Note also that when a pull up resistor is selected the port pins are held at the high level and not placed in a high impedance state even when the SPL bit is set to 1 Table 9 4 4 lists the states of the port 1 pins Table 9 ...

Page 197: ... register DDR2 Port 2 Pins The port 2 I O pins are also used as resource I O pins The pins cannot be used as general purpose I O port pins when they are used as resource I O pins Table 9 5 1 lists the port 2 pins See 1 7 I O Circuit Types for information on the circuit types Table 9 5 1 Port 2 Pins Port Pin Port function Resource function I O form Circuit type Input Output Port 2 P20 TIN1 P20 Gene...

Page 198: ... register correspond to the port 2 pins on a one to one basis Table 9 5 2 lists the port 2 pins and their corresponding register bits Internal data bus Port data register PDR PDR read PDR write Output latch DDR read DDR write Direction latch Port data direction register DDR Pin Standby control SPL 1 Resource output Resource output enable Resource input Table 9 5 2 Port 2 Pins and their Correspondi...

Page 199: ...To use a resource having input pins reset the DDR2 register bit corresponding to each resource input pin to 0 to place the port in input mode Table 9 5 3 lists the functions of the port 2 registers Table 9 5 3 Port 2 Register Functions Register Data During reading During writing Read Write Address Initial value Port 2 data register PDR2 0 The pin is at the low level The output latch is loaded with...

Page 200: ...n specify output mode in the DDR register Port operation in input mode Resetting a bit of the DDR2 register to 0 places the corresponding port pin in input mode In input mode the output buffer is turned off and the pins are placed in a high impedance state Data written to the PDR2 register in input mode is held in the output latch of the PDR but not output to the port pins The PDR2 register can be...

Page 201: ...rol register LPMCR is already 1 when the port is shifted to stop or time base timer mode the port pins are placed in a high impedance state This is because the output buffer is turned off forcibly regardless of the value in the DDR2 register Note that the inputs are fixed at a certain level to prevent leakage due to an open circuit Table 9 5 4 lists the states of the port 2 pins Table 9 5 4 States...

Page 202: ... pins are also used as resource output pins Therefore the pins cannot be used as general purpose I O port pins when they are used as resource I O pins Table 9 6 1 lists the port 3 pins See 1 7 I O Circuit Types for information on the circuit types Table 9 6 1 Port 3 Pins Port Pin Port function single chip mode Resource function I O form Circuit type Input Output Port 3 P30 RTO0 P30 General purpose...

Page 203: ...each register correspond to the port 3 pins on a one to one basis Table 9 6 2 lists the port 3 pins and their corresponding register bits Internal data bus Port data register PDR PDR read PDR write Output latch DDR read DDR write Direction latch Port data direction register DDR Pin Standby control SPL 1 Resource output Resource output enable Table 9 6 2 Port 3 pins and their Corresponding Register...

Page 204: ... as the resource output enable bit corresponding to the pins is set Table 9 6 3 lists the functions of the port 3 registers Table 9 6 3 Port 3 Register Functions Register Data During reading During writing Read Write Address Initial value Port 3 data register PDR3 0 The pin is at the low level The output latch is loaded with 0 When the pin functions as an output port the pin is set to the low leve...

Page 205: ...t of the DDR3 register to 0 places the corresponding port pin in input mode In input mode the output buffer is turned off and the pins are placed in a high impedance state Data written to the PDR3 register in input mode is held in the output latch of the PDR but not output to the port pins The PDR3 register can be accessed in read mode to read the level value 0 or 1 at the port pins Port operation...

Page 206: ...ss of the value in the DDR3 register Note that the inputs are fixed at a certain level to prevent leakage due to an open circuit Table 9 6 4 lists the states of the port 3 pins Table 9 6 4 States of Port 3 Pins Pin Normal operation Sleep mode Stop mode or time base timer mode SPL 0 Stop mode or time base timer mode SPL 1 P30 RTO0 to P37 PPG0 General purpose I O port General purpose I O port Genera...

Page 207: ...R4 Port 4 Pins The port 4 I O pins are also used as resource I O pins The pins cannot be used as general purpose I O port pins when they are used as resource I O pins Table 9 7 1 lists the port 4 pins See 1 7 I O Circuit Types for information on the circuit types Table 9 7 1 Port 4 Pins Port Pin Port function single chip mode Resource function I O form Circuit type Input Output Port 4 P40 SIN0 P40...

Page 208: ...ch register correspond to the port 4 pins on a one to one basis Table 9 7 2 lists the port 4 pins and their corresponding register bits Port data register PDR PDR read PDR write Output latch DDR read DDR write Direction latch Port data direction register DDR Pin Standby control SPL 1 Resource output Resource output enable Internal data bus Resource input Table 9 7 2 Port 4 Pins and their Correspon...

Page 209: ...corresponding to each resource input pin to 0 to place the port in input mode Table 9 7 3 lists the functions of the port 4 registers Table 9 7 3 Port 4 Register Functions Register Data During reading During writing Read Write Address Initial value Port 4 data register PDR4 0 The pin is at the low level Setting an DDR5 bit to 0 enables the pin for a high impedance Setting an DDR5 bit to 1 enables ...

Page 210: ...specify output mode in the DDR register Port operation in input mode Resetting a bit of the DDR4 register to 0 places the corresponding port pin in input mode In input mode the output buffer is turned off and the pins are placed in a high impedance state Data written to the PDR4 register in input mode is held in the output latch of the PDR but not output to the port pins The PDR4 register can be a...

Page 211: ...rol register LPMCR is already 1 when the port is shifted to stop or time base timer mode the port pins are placed in a high impedance state This is because the output buffer is turned off forcibly regardless of the value in the DDR4 register Note that the inputs are fixed at a certain level to prevent leakage due to an open circuit Table 9 7 4 lists the states of the port 4 pins Table 9 7 4 States...

Page 212: ...register ADER Port 5 Pins The port 5 I O pins are also used as analog input pins The pins cannot be used as general purpose I O port pins when they are used for analog input Similarly the port 5 I O pins cannot be used for analog input when they are used as a general purpose I O port Table 9 8 1 lists the port 5 pins See 1 7 I O Circuit Types for information on the circuit types Table 9 8 1 Port 5...

Page 213: ...he PDR5 register is 0 Port 5 Registers Port 5 registers are PDR5 DDR5 and ADER The bits making up each register correspond to the port 5 pins on a one to one basis Table 9 8 2 lists the port 5 pins and their corresponding register bits Internal data bus ADER PDR read PDR write Output latch DDR read DDR write Direction latch Port data direction register DDR Pin Standby control SPL 1 Port data regis...

Page 214: ... for general purpose I O Note If a signal at an intermediate level is input in port I O mode input leak current flows Therefore for a pin used for analog input be sure to set the corresponding ADER bit to 1 for analog input Reference When the CPU is reset the DDR5 register is reset to 0 and the ADER register is set to 1 for analog input Table 9 8 3 lists the functions of the port 5 registers Table...

Page 215: ...utput therefore write the output data to the PDR register then specify output mode in the DDR register Port operation in input mode Resetting a bit of the DDR5 and ADER register to 0 places the corresponding port pin in input mode In input mode the output buffer is turned off and the pins are placed in a high impedance state Data written to the PDR5 register in input mode is held in the output lat...

Page 216: ...d off forcibly Note that the inputs are fixed at a certain level to prevent leakage due to an open circuit Table 9 8 4 lists the states of the port 5 pins Table 9 8 4 States of Port 5 Pins Pin Normal operation Sleep mode Stop mode or time base timer mode SPL 0 Stop mode or time base timer mode SPL 1 P50 AN0 to P57 AN7 General purpose I O port General purpose I O port General purpose I O port Input...

Page 217: ... I O pins P60 SIN1 to P63 INT7 Port 6 data register PDR6 Port 6 data direction register DDR6 Port 6 Pins The port 6 I O pins are also used as resource I O pins The pins cannot be used as general purpose I O port pins when they are used as resource I O pins Table 9 9 1 lists the port 6 pins See 1 7 I O Circuit Types for information on the circuit types Table 9 9 1 Port 6 Pins Port Pin Port function...

Page 218: ...he port 6 pins and their corresponding register bits Port data register PDR PDR read PDR write Output latch DDR read DDR write Direction latch Port data direction register DDR Pin Standby control SPL 1 Resource output Resource output enable Internal data bus Resource input External interrupt enable Table 9 9 2 Port 6 Pins and their Corresponding Register Bits Port Register bits and corresponding p...

Page 219: ...se a resource having input pins reset the DDR6 register bit corresponding to each resource input pin to 0 to place the port in input mode Table 9 9 3 lists the functions of the port 6 registers Table 9 9 3 Port 6 Register Functions Register Data During reading During writing Read Write Address Initial value Port 6 data register PDR6 0 The pin is at the low level The output latch is loaded with 0 W...

Page 220: ...n specify output mode in the DDR register Port operation in input mode Resetting a bit of the DDR6 register to 0 places the corresponding port pin in input mode In input mode the output buffer is turned off and the pins are placed in a high impedance state Data written to the PDR6 register in input mode is held in the output latch of the PDR but not output to the port pins The PDR6 register can be...

Page 221: ...l register LPMCR is already 1 when the port is shifted to stop or time base timer mode the port pins are placed in a high impedance state This is because the output buffer is turned off forcibly regardless of the value in the DDR6 register Note that the inputs are fixed at a certain level to prevent leakage due to an open circuit Table 9 9 4 lists the states of the port 6 pins Table 9 9 4 States o...

Page 222: ...ment pins Figure 9 10 1 is an example of connecting the eight segment LED to the MB90460 465 series ports Figure 9 10 1 Example of Eight segment LED Connection Coding example PDR EQU 000000H PDR1 EQU 000001H DDR0 EQU 000010H DDR1 EQU 000011H Main program CODE CSEG START Initialization MOV I PDR0 00000000B Puts P00 at a low level XXXXXXX0B MOV I DDR0 11111111B Puts all port 0 bits in output mode MO...

Page 223: ...204 CHAPTER 9 I O PORT ...

Page 224: ... base timer 10 1 Overview of the Time base Timer 10 2 Configuration of the Time base Timer 10 3 Time base Timer Control Register TBTC 10 4 Time base Timer Interrupts 10 5 Operation of the Time base Timer 10 6 Usage Notes on the Time base Timer 10 7 Sample Program for the Time base Timer Program ...

Page 225: ...for the watchdog timer Interval Timer Function The interval timer function repeatedly generates an interrupt request at a given interval An interrupt request is generated when the interval timer bit for the time base counter overflows The interval timer bit interval can be selected from four types Table 10 1 1 lists the intervals for the time base timer Table 10 1 1 Intervals for the Time base Tim...

Page 226: ... soon as oscillation starts Table 10 1 2 Clock Cycle Time supplied from the Time base Timer Clock destination Clock cycle time Remarks Oscillation stabilization time 213 HCLK Approx 2 0 ms Oscillation stabilization time for ceramic vibrator 215 HCLK Approx 8 2 ms Oscillation stabilization time for crystal vibrator 218 HCLK Approx 65 4 ms Watchdog timer 212 HCLK Approx 1 0 ms Count up clock for wat...

Page 227: ...LPMCR STP 1 Interval timer selector Selects one of four outputs of the time base timer counter An overflow of the selected bit becomes an interrupt cause Time base timer control register TBTC Selects the interval clears the counter controls an interrupt request and checks the status OF Overflow HCLK Oscillation clock 1 Switching of the machine clock from the oscillation clock to the PLL clock 2 In...

Page 228: ... During writing During reading During writing 0 0 0 212 HCLK Approx 1 0 ms 214 HCLK Approx 4 1 ms Clearing of the time base timer counter and TBOF bit No change no effect on other bits The read value is always 1 Interrupt request output disabled Interrupt request output enabled Clearing of this bit No overflow from the specified bit No change no effect on other bits Overflow from the specified bit...

Page 229: ...E are 1 an interrupt request is output During writing this bit is cleared with 0 If 1 is written the bit does not change and there is no effect Note To clear the TBOF bit disable the time base timer interrupt by specifying the TBIE bit or processor status PS ILM bit The TBOF bit is cleared by writing 0 by a transition to stop mode by clearing of the time base timer with the TBR bit or by a reset b...

Page 230: ...ess of the TBIE bit value Note Clear the interrupt request flag bit TBTC TBOF while a time base timer interrupt is disabled by setting the TBIE bit or the processor status PS ILM bit Reference When the TBOF bit is 1 if the TBIE bit status is switched from disable to enable 0 1 an interrupt request occurs immediately Time base Timer Interrupts and EI2 OS Table 10 4 1 lists the time base timer inter...

Page 231: ...ng of the Time base Timer The time base timer counter continues counting up in synchronization with the internal count clock one half of the oscillation clock as long as the clock is being oscillated When the counter is cleared TBR 0 it counts up from 0 When the interval timer bit overflows the interrupt request flag bit TBOF is set to 1 If interrupt request output has been enabled TBIE 1 an inter...

Page 232: ...e oscillation stabilization times Clock Supply Function The time base timer supplies clocks to the watchdog timer Clearing of the time base counter affects operation of the watchdog timer Table 10 5 1 Time base Timer Counter Clearing and Oscillation Settling Times Operation Counter clear TBOF clear Oscillation settling time TBTC Writing of 0 to TBR O O Power on reset O O Oscillation clock oscillat...

Page 233: ... in main stop mode After oscillator operation starts the operating clock supplied by the time base timer is used to take the oscillation stabilization wait time of the main clock An appropriate oscillation stabilization wait time must be selected based on the type of oscillating element connected to the main clock oscillator clock generation section See 5 5 Oscillation Stabilization Wait Interval ...

Page 234: ...n time Figure 10 6 1 Time base Timer Operations Counter value 3FFFFH Oscillation stabilization delay overflow 0000H Power on reset optional CPU operation starts Interval cycle TBTC TBC1 TBC0 11B Cleared by the interrupt handling routine Cleared by transition to stop mode Counter clear TBTC TBR 0 TBOF bit TBIE bit SLP bit STBC register STP bit STBC register Sleep mode Releasing of interval interrup...

Page 235: ...ister TBTC EQU 0000A9H Time base timer control register TBOF EQU TBTC 3 Interrupt request flag bit Main program CODE CSEG START Assumes that stack pointer SP has already been initialized AND CCR 0BFH Disables interrupts MOV I ICR12 00H Interrupt level 0 highest MOV I TBTC 10010000B Fixes upper 3 bits Enables interrupts and clears TBOF Clears counter Selects interval 212 HCLK MOV ILM 07H Sets PS IL...

Page 236: ...7 CHAPTER 10 TIME BASE TIMER Vector setting VECT CSEG ABS 0FFH ORG 0FF6CH Sets vector for interrupt 36 24H DSL WARI ORG 0FFDCH Sets reset vector DSL START DB 00H Sets single chip mode VECT ENDS END START ...

Page 237: ...218 CHAPTER 10 TIME BASE TIMER ...

Page 238: ...d operation of the watchdog timer 11 1 Overview of the Watchdog Timer 11 2 Configuration of the Watchdog Timer 11 3 Watchdog Timer Control Register WDTC 11 4 Operation of the Watchdog Timer 11 5 Usage Notes on the Watchdog Timer 11 6 Sample Program for the Watchdog Timer ...

Page 239: ...ycle count depend on the clear timing The interval is 3 5 to 4 5 times longer than the cycle of the count clock time base timer supply clock See 11 4 Operation of the Watchdog Timer Note The watchdog counter consists of a 2 bit counter that uses the carry signals of the time base timer as count clocks Therefore if the time base timer is cleared the watchdog reset generation time may become longer ...

Page 240: ...t generation time Watchdog counter 2 bit counter This 2 bit up counter uses the time base timer output as the count clock Watchdog reset generator Used to generate the reset signal by an overflow of the watchdog counter Counter clear circuit Used to clear the watchdog counter and to control the operation or stopping of the counter Watchdog timer control register WDTC Used to activate or clear the ...

Page 241: ... value X XXX111B PONR WRST ERST SRST WTE WT1 WT0 TBTC WT1 WT0 Interval selection bit for 4 MHz HCLK Interval Minimum Maximum Oscillation clock cycle count 0 0 0 Approx 3 58 ms Approx 4 61 ms Power on Watchdog timer External pin RSTX input RST bit software reset 214 211 cycle 216 213 cycle 218 215 cycle 221 218 cycle Approx 14 33 ms HCLK Oscillation clock Approx 18 3 ms Approx 57 23 ms Approx 73 73...

Page 242: ...d At power on the contents of the bits other than the PONR bit are not guaranteed Therefore when the PONR bit is 1 ignore the contents of the bits other than the PONR bit bit2 WTE Watchdog timer control bit When 0 is written to this bit the watchdog timer is activated first write after reset or the 2 bit counter is cleared second or subsequent write after reset Writing 1 does not affect operation ...

Page 243: ...wn reset Clearing the watchdog timer When a second or subsequent 0 is written to the WTE bit the 2 bit counter of the watchdog timer is cleared If the counter is not cleared within the time interval it overflows and a watchdog reset occurs The watchdog counter is cleared by reset generation sleep mode or stop mode transition to clock mode Intervals for the watchdog timer Figure 11 4 2 shows the re...

Page 244: ...it is cleared immediately before the count clock rises Count start Counter clearing Count clock a Divide by two value b Divide by two value c Count enabling 7 x count clock cycle 2 WTE bit clearing Watchdog reset generation Reset signal d 9 x count clock cycle 2 Reset signal d WTE bit clearing Watchdog reset generation Maximum interval When the WTE bit is cleared immediately after the count clock ...

Page 245: ...the interval the watchdog timer interval may become longer than the setting time when the time base timer is cleared Selecting the interval The interval can be set when the watchdog timer is activated Data written during operations other than activation is ignored Notes on program creation When a program that repeatedly clears the watchdog timer in the main loop is created the processing time of t...

Page 246: ...e WDTC EQU 0000A8H Watchdog timer control register WTE EQU WDTC 2 Watchdog control bit Main program CODE CSEG START Assumes that stack pointer SP has already been initialized WDG_START MOV WDTC 00000011B Activates watchdog timer Selects the interval 221 218 cycle Main loop MAIN CLRB I WTE Clears watchdog timer Clears this bit regularly User processing JMP MAIN Loops in less time than the watchdog ...

Page 247: ...228 CHAPTER 11 WATCHDOG TIMER ...

Page 248: ... Overview of the 16 bit Reload Timer 12 2 Block Diagram of the 16 bit Reload Timer 12 3 16 bit Reload Timer Pins 12 4 16 bit Reload Timer Registers 12 5 16 Bit Reload Timer Interrupts 12 6 Operation of the 16 bit Reload Timer 12 7 Usage Notes on the 16 bit Reload Timer 12 8 Sample Programs for the 16 bit Reload Timer ...

Page 249: ...els Overview of the 16 bit Reload Timer 16 bit reload timer operating modes Table 12 1 1 lists the operating modes of the 16 bit reload timer Internal Clock Mode Internal clock mode allows selection of one of three types of internal clock for the following operations Software trigger operation When 1 is written to the TRG bit of the timer control status register TMCSRL0 TMCSRL1 counting starts Tri...

Page 250: ...s Table 12 1 2 lists the intervals for the 16 bit reload timer Single shot mode When an underflow from 0000H to FFFFH occurs during counting down counting stops causing an interrupt to occur for the underflow condition During counter operation a rectangular waveform that indicates when the count is in progress can be output from the TO0 and TO1 pins References 16 bit reload timer 0 can be used to ...

Page 251: ...table address EI2OS Register name Address Lower Middle Upper 16 bit reload timer 0 1 30 1EH ICR09 0000B9H FFFF84H FFFF85H FFFF86H O 16 bit reload timer 1 2 18 12H ICR03 0000BAH FFFFB4H FFFFB5H FFFB6H O Can be used 1 The same interrupt number as that for 16 bit reload timer 0 underflow is assigned to 16 bit timer 0 1 2 counter borrow 2 The same interrupt number as that for 16 bit reload timer 1 und...

Page 252: ...load operation when the timer is started and when an underflow occurs F2MC 16LX bus 16 bit reload register Reload signal Reload control circuit 16 bit timer register Count clock generation circuit Machine clock Pre scaler Clear Gate input Valid clock judgment circuit Wait signal Internal clock Pin Input control circuit External clock Clock selector Select signal Invert Output control circuit Outpu...

Page 253: ... is read from this register during a read operation 16 bit reload register TMRD0 TMRD1 The interval for the 16 bit reload timer is set in this register The setting value of this register is loaded into the 16 bit timer register and decremented Timer control status register TMCSR0 TMCSR1 This register selects the count clock of the 16 bit reload timer and the operating mode sets operating condition...

Page 254: ...Standby control Settings required for pins P15 INT5 TIN0 Port 1 input output external interrupt input timer input CMOS output CMOS hysteresis input Selection allowed Available Setting for the input port DDR1 bit15 0 P16 INT6 TO0 Port 1 input output external interrupt input timer output Setting for timer output enable TMCSRL0 OUTE 1 P20 TIN1 Port 2 input output timer input Setting for the input por...

Page 255: ...0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 Initial value Read write MOD0 OUTE OUTL RELD INTE UF CNTE TRG 15 14 13 12 11 10 9 8 R W X R W X R W X R W X R W X R W X R W X R W X D15 D14 D13 D12 D11 D10 D09 D08 7 6 5 4 3 2 1 0 16 bit Timer Register 16 bit Reload Register Upper 16 bit Timer Register 16 bit Reload Register Lower TMR0 TMRD0 TMR0 TMRD0 Initial value Read write R W X R W X R W X R W X R W...

Page 256: ...1 MOD2 MOD1 MOD0 X X X X 0 0 1 1 0 1 0 1 TMCSR L TMCSRH0 000083H TMCSRH1 000087 H CSL1 CSL0 0 0 1 1 0 1 0 1 00000B R W X Address Initial value Read Write Initial value Undefined Not used Machine cycle Value in parentheres indicates the value when machine clock is 16MHz Operating mode selection bit Input pin function Valid edge and level Trigger disabled Trigger input Gate input Internal clock mode...

Page 257: ...ing mode selection bits In internal clock mode The MOD2 bit is used to select input pin functions When the MOD2 bit is 0 the input pin is used as a trigger input pin so that whenever a valid edge is input the contents of the reload register are loaded into the counter and counting continues The MOD1 and MOD0 bits are used to select the type of valid edge When the MOD2 bit is 1 the input pin become...

Page 258: ...nable underflow interrupt 1 Underflow interrupt enable bit RELD 0 Single shot mode Reload mode 1 Reload selection bit CNTE 0 Counting stopped Counting enabled wait for the start trigger 1 Count enable bit UF During reading During writing Underflow interrupt request flag bit 0 Without counter underflow With counter underflow This bit is cleared No effect 1 OUTL In single shot mode RELD 0 In reload ...

Page 259: ...it is 0 the timer is in single shot mode Counting stops when an underflow occurs bit3 INTE Interrupt request enable bit This bit enables or disables underflow interrupt request to the CPU When this bit and the underflow interrupt request flag UF bit are 1 the timer outputs an interrupt request bit2 UF Underflow interrupt request flag bit This bit is set to 1 when a counter underflow occurs Writing...

Page 260: ...s TMCSRL0 TMCSRL1 CNTE 0 Notes This register is able to read the count value even during counting It should always be read with a word transfer instruction MOVW A 003AH etc Although the 16 bit timer register TMR0 TMR1 is a read only register it is allocated to the same address as the address of the write only 16 bit reload register TMRD0 TMRD1 Accordingly writing to this register has no effect on ...

Page 261: ...n an underflow occurs and counting down continues In single shot mode the counter stops at FFFFH when an underflow occurs Notes Write a value to this register in the counter stop TMCSRL0 TMCSRL1 CNTE 0 state Also always use a word transfer instruction MOVW 003AH A etc to write a value to this register Although the 16 bit reload register TMRD0 TMRD1 is functionally a write only register it is alloc...

Page 262: ...owever EI2OS is available only when other peripheral functions sharing the interrupt control register ICR do not use interrupts For example when 16 bit reload timer 0 uses EI2 OS interrupts of the waveform generator 16 bit timer 0 1 2 counter borrow must be disabled Table 12 5 1 Interrupt Control Bits and Interrupt Causes of the 16 bit Reload Timer 16 bit reload timer 0 16 bit reload timer 1 Inter...

Page 263: ... setting The setting shown in Figure 12 6 2 is required to operate this timer as an event counter Figure 12 6 2 Event Counter Mode Setting CSL1 CSL0 MOD2 MOD1MOD0OUTE OUTL RELD INTE UF CNTE TRG Set the initial value reload value of the counter TMCSR0 TMCSR1 TMRD0 TMRD1 O O O O O O O O 1 O Other than 11 O Used 1 Set to 1 CSL1 CSL0 MOD2 MOD1MOD0OUTE OUTL RELD INTE UF CNTE TRG Set the initial value r...

Page 264: ...by hardware State transitions by register access Load complete TIN Input disabled TO General purpose port The counter value is retained when the counter stops Immediately after a reset it is undefined TIN Functions as TIN TO Functions as TO TIN Only trigger input enabled TO Output initial value retained when the counter stops Immediately after a reset it is undefined and remains so until a value i...

Page 265: ...ling of counting When an underflow of the counter value from 0000H to FFFFH occurs the value of the 16 bit reload register TMRD0 TMRD1 is loaded into the counter and counting continues If the underflow interrupt flag TMCSRL0 TMCSRL1 UF bit is set to 1 and the underflow interrupt enable TMCSRL0 TMCSRL1 INTE bit is 1 an interrupt request is generated The timer can also output from the TO0 TO1 pin a ...

Page 266: ...lected is input to the TIN0 TIN1 pin counting is done Figure 12 6 6 shows gate input in reload mode Figure 12 6 6 Count Operation in Reload Mode Software Trigger and Gate Input Operation Note Specify 2 φ or more for the width of the trigger pulse input to the TIN0 TIN1 pin Count clock Counter Data load signal UF bit CNTE bit TIN pin TO pin Reload data Reload data Reload data Reload data T Machine ...

Page 267: ...bling of counting When an underflow of the counter value from 0000H to FFFFH occurs the counter stops in the FFFFH state If the underflow interrupt flag TMCSRL0 TMCSRL1 UF bit is set to 1 and the underflow interrupt enable TMCSRL0 TMCSRL1 INTE bit is 1 an interrupt request is generated The timer can also output from the TO0 TO1 pin a rectangular waveform indicating that counting is in progress Sof...

Page 268: ...d is input to the TIN0 TIN1 pin counting is done Figure 12 6 9 shows gate input operation in single shot mode Figure 12 6 9 Count Operation in Single shot Mode Software Trigger and Gate Input Operation Note Specify 2 φ or more for the width of the trigger pulse input to the TIN0 TIN1 pin Count clock Counter Reload data Data load signal UF bit CNTE bit TIN bit TO pin Wait for trigger input Reload d...

Page 269: ...taneously counting is started simultaneously with the enabling of counting Operation in reload mode When an underflow of the counter value from 0000H to FFFFH occurs the value of the reload register TMRD0 TMRD1 is loaded into the counter and counting continues If the underflow interrupt flag TMCSRL0 TMCSRL1 UF bit is set to 1 and the underflow interrupt enable bit TMCSRL0 TMCSRL1 INTE is 1 an inte...

Page 270: ...is generated The timer can also output from the TO0 TO1 pin a rectangular waveform indicating that counting is in progress Figure 12 6 11 shows counting in single shot mode Figure 12 6 11 Counter Operation in Single shot Mode Event Count Mode Note Specify 4 φ or more for the H and L widths of the clock input to the TIN0 TIN1 pin TIN pin Counter Reload data Data load signal UF bit CNTE bit TRG bit ...

Page 271: ...dir etc Change the CSL1 and CSL0 bits of the timer control status register TMCSRH0 TMCSRH1 when the counter has stopped TMCSRL0 TMCSRL1 CNTE 0 Notes about interrupts When the UF bit of the timer control status register TMCSRL0 TMCSRL1 is set to 1 and an interrupt request is enabled TMCSRL0 TMCSRL1 INTE 1 control cannot be returned from interrupt processing Always clear the UF bit Since the 16 bit ...

Page 272: ...ntrol register for the 16 bit reload timer TMCSR EQU 000082H Timer control status register TMR EQU 000084H 16 bit timer register TMRD EQU 000084H 16 bit reload register UF EQU TMCSR 2 Interrupt request flag bit CNTE EQU TMCSR 1 Counter operation enable bit TRG EQU TMCSR Software trigger bit Main program CODE CSEG START Assumes that stack pointer SP has already been initialized AND CCR 0BFH Interru...

Page 273: ...e rising edge of the pulse input to the external event input pin is counted 10 000 times with 16 bit reload timer counter 0 an interrupt is generated The timer operates in single shot mode External trigger input selects the rising edge EI2 OS is not used Coding example ICR09 EQU 0000B9H Interrupt control register for the 16 bit reload timer TMCSR EQU 000082H Timer control status register TMR EQU 0...

Page 274: ...1B Counter operation external event input rising Disables external output Selects single shot mode and enables interrupts Clears interrupt flag starts counter MOV ILM 07H Sets ILM in PS to level 7 OR CCR 40H Interrupt enable LOOP MOV A 00H Endless loop MOV A 01H BRA LOOP Interrupt program WARI CLRB I UF Clears interrupt request flag User processing RETI Returns from interrupt CODE ENDS Vector sett...

Page 275: ...256 CHAPTER 12 16 BIT RELOAD TIMER ...

Page 276: ... PPG Timer 13 1 Overview of 16 bit PPG Timer 13 2 Block Diagram of 16 bit PPG Timer 13 3 16 bit PPG Timer Pins 13 4 16 bit PPG Timer Registers 13 5 16 bit PPG Timer Interrupts 13 6 Operation of 16 bit PPG Timer 13 7 Usage Notes on the 16 bit PPG Timer 13 8 Sample Programs for the 16 bit PPG Timer ...

Page 277: ...control register and a PPG output pin This module can be used to output pulses synchronized by software trigger or GATE signal from Multi functional timer refer to Multi functional Timer in chapter 14 8 types of counter operation clock φ φ 2 φ 4 φ 8 φ 16 φ 32 φ 64 φ 128 can be selected φ is the machine clock An interrupt is generated when there is a trigger or an counter borrow or when PPG rising ...

Page 278: ...own counter Comparator S Q R Interrupt selection Prescaler Machine clock φ MDSE PGMS OSEL POEN PPG0 multi functional timer or PPG1 multi pulse generator or PPG2 Pin P37 PPG0 or P36 PPG1 or P46 PPG2 Interrupt IRS1 IRS0 IRQF IREN Down Counter Register 0 1 2 CKS2 CKS1 CKS0 F 2 MC 16LX bus 1 128 STOP Edge detection STGR CNTE RTRG 14 16 32 GATE from multi functional timer for PPG ch 0 only for PPG ch 1...

Page 279: ...able 13 3 1 16 bit PPG Timer Pins Pin name Pin function I O format Standby control Settings required for pins P37 PPG0 Port 3 input output PPG0 output CMOS output CMOS input Available Setting for the PPG timer 0 output PNCTL0 POEN 1 P36 PPG1 Port 3 input output PPG1 output Setting for PPG timer 1 output enable PNCTL1 POEN 1 P46 PPG2 Port 4 input output PPG2 output CMOS output CMOS hysteresis input...

Page 280: ...agram of the 16 bit PPG Timer 2 Pin Port data register PDR PDR read PDR write Output latch DDR read DDR write Direction latch Port data direction register DDR Pin Standby control SPL 1 Resource output Resource output enable Internal data bus Resource input ...

Page 281: ... 2 00004BH PCSR0 to W X W X W X W X W X W X W X W X Initial value Read write Address ch 0 00003AH ch 1 000042H ch 2 00004AH W X W X W X W X W X W X W X W X Initial value Read write PCSR0 to 15 14 13 12 11 10 9 8 PPG Duty Setting Buffer Register Upper 7 6 5 4 3 2 1 0 PPG Duty Setting Buffer Register Lower Address ch 0 00003DH ch 1 000045H ch 2 00004DH PDUT0 to W X W X W X W X W X W X W X W X Initia...

Page 282: ...pper Address ch 0 00003EH ch 1 000046H ch 2 00004EH PCNTL0 to R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 Initial value Read write R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 Initial value Read write PCNTH0 to Address ch 0 00003FH ch 1 000047H ch 2 00004FH CNTE STGR MDSE RTRG CKS1 CKS0 PGMS CKS2 IREN IRQF IRS1 IRS0 POEN OSEL bit bit PCNTL2 PCNTH2 ...

Page 283: ...es of the 16 bit down counter The initial value of them are all 1 Word access to these register are recommended These registers are read only 15 14 13 12 11 10 9 8 PPG Down Counter Register Upper 7 6 5 4 3 2 1 0 PPG Down Counter Register Lower Address ch 0 000039H ch 1 000041H ch 3 000049H PDCR0 to R 1 R 1 R 1 R 1 R 1 R 1 R 1 R 1 Initial value Read write Address ch 0 000038H ch 1 000040H ch 3 0000...

Page 284: ...Data transfer from period setting buffer register to period setting register will be at counter borrow or trigger or retrigger if enabled Note In case of updating period setting buffer register duty setting buffer register must be written after writing to period setting buffer register Only updating period setting buffer register is prohibited 15 14 13 12 11 10 9 8 PPG Period Setting Buffer Regist...

Page 285: ...fer register to duty setting register is at counter borrow or trigger or retrigger if enabled Setting the same value in both the period setting register and duty setting register outputs all H s for normal polarity and all L s for inverted polarity The output of the PPG is indeterminate if PCSR PDUT Note Duty setting buffer register can be written in the case of not updating period setting buffer ...

Page 286: ...S0 PGMS 00000000B R W R W R W R W R W R W R W R W PGMS PPG output mask enable bit 0 PPG output masking disabled 1 PPG output masking enabled CKS2 CKS1 CKS0 Counter clock selection bits 0 0 0 φ 62 5 ns φ 16 MHz 0 0 1 φ 2 125 ns φ 16 MHz 0 1 0 φ 4 250 ns φ 16 MHz 0 1 1 φ 8 500 ns φ 16 MHz 1 0 0 φ 16 1 µs φ 16 MHz 1 0 1 φ 32 2 µs φ 16 MHz 1 1 0 φ 64 4 µs φ 16 MHz 1 1 1 φ 128 8 µs φ 16 MHz φ Machine c...

Page 287: ... of PPG during operation When this bit is 0 retriggering function is disabled When this bit is 1 retriggering function is enabled bit11 to bit9 CKS2 to CKS0 Counter clock selection bits This bit are used to select the operation clock for 16 bit PPG timer bit8 PGMS PPG output mask enable bit This bit is used to mask the PPG output to specific level regardless of the mode setting PCNTH MDSE period s...

Page 288: ...7 P36 P46 1 PPG output pin PPG0 PPG1 PPG2 IRS1 IRS0 Interrupt type 0 0 Gate trigger channel 0 only Software trigger Retigger 0 1 Counter borrow 1 0 PPG output rising in normal polarity or PPG output falling in inverted polarity duty match 1 1 Counter borrow or PPG output rising in normal polarity or PPG output falling in inverted polarity IRQF PPG interrupt request flag Read Write 0 No PPG interru...

Page 289: ... no effect In read modify write operation 1 is always read This bit is also cleared when EI2 OS is activated bit3 bit2 IRS1 IRS0 Interrupt selection bit These bits are used to select interrupt condition of the PPG timer bit1 POEN Output enable bit This bit enables or disables output from the PPG output pin When this bit is 0 the pin functions as a general purpose port When this bit is 1 the pin fu...

Page 290: ...S0 Interrupt cause PCNTL0 IRS1 IRS0 00 gate trigger software trigger retrigger of 16 bit down counter ch 0 PCNTL1 IRS1 IRS0 00 software trigger retrigger of 16 bit down counter ch 1 PCNTL2 IRS1 IRS0 00 software trigger retrigger of 16 bit down counter ch 2 PCNTL0 IRS1 IRS0 01 counter borrow of 16 bit down counter ch 0 PCNTL1 IRS1 IRS0 01 counter borrow of 16 bit down counter ch 1 PCNTL2 IRS1 IRS0 ...

Page 291: ...h must be disabled Table 13 5 2 16 bit PPG Timer Interrupts and EI2OS Channel Interrupt number Interrupt control register Vector table address EI2OS Register name Address Lower Middle Upper 16 bit PPG timer 0 1 14 0EH ICR01 0000B1H FFFFC4H FFFFC5H FFFFC6H O 16 bit PPG timer 1 2 16 10H ICR02 0000B2H FFFFBCH FFFFBDH FFFFBEH 16 bit PPG timer 2 3 32 20H ICR10 0000BAH FFFF7CH FFFF7DH FFFF7EH 1 The same...

Page 292: ...period of the output pulses can be controlled by setting PCSR and the duty ratio controlled by setting PDUT a Retriggering is disabled PCNTH RTRG 0 Figure 13 6 1 Retriggering is disabled in PWM Mode b Retriggering is enabled PCNTH RTRG 1 Figure 13 6 2 Retriggering is enabled in PWM Mode m n 0 1 n 1 T ns 2 m 1 T ns T Count clock period m PCSR value n PDUT value PPG 1 2 normal polarity inverted pola...

Page 293: ...isabled in Single shot Mode b Retriggering is enabled PCNTH RTRG 1 Figure 13 6 4 Retriggering is enabled in Single shot Mode m n 0 Trigger is ignored 1 n 1 T ns 2 m 1 T ns T Count clock period m PCSR value n PDUT value 1 2 normal polarity inverted polarity PPG PPG Software trigger Counter value Time Rising edge detected m n 0 1 n 1 T ns 2 m 1 T ns T Count clock period m PCSR value n PDUT value 1 2...

Page 294: ... IRS1 IRS0 Gate trigger for PPG channel 0 only or software trigger or retrigger Counter borrow Duty match occurs when PPG output rising in normal polarity or PPG output falling in inverted polarity Counter borrow or duty match Figure 13 6 6 PPG Interrupt Timing m n 0 1 n 1 T ns 2 m 1 T ns T Count clock period m PCSR value n PDUT value PPG 1 2 normal polarity inverted polarity Time Counter value Ga...

Page 295: ...T not greater than period setting buffer register PCSR otherwise the output of PPG is indeterminate Change the CKS2 CKS1 and CKS0 bits of the control status register PCNTH when the PPG is stopped PCNTH CNTE 0 Notes about interrupts When the IRQF bit of the PPG control status register PCNTL is set to 1 and an interrupt request is enabled PCNTL IREN 1 control cannot be returned from interrupt proces...

Page 296: ...0003AH PPG period setting register PDUT0 EQU 00003CH PPG duty setting register PCNT0 EQU 00003EH PPG control status register IRQF EQU PCNT0 4 Interrupt request flag bit Main program CODE CSEG START Assumes that stack pointer SP has already been initialized AND CCR 0BFH Interrupt disable MOV I ICR01 00H Interrupt level 0 strongest MOVW I PCSR0 0063H Sets the period of the PPG output MOVW I PDUT0 00...

Page 297: ...IRQF Clears interrupt request flag User processing RETI Returns from interrupt CODE ENDS Vector setting VECT CSEG ABS 0FFH ORG 0FFC4H Sets vector for interrupt 14 0EH DSL WARI ORG 0FFDCH Sets reset vector DSL START DB 00H Sets single chip mode VECT ENDS END START ...

Page 298: ...rview of Multi functional Timer 14 2 Block Diagram of Multi functional Timer 14 3 Multi functional Timer Pins 14 4 Registers of Multi functional Timer 14 5 Multi functional Timer Interrupts 14 6 Operation of Multi functional Timer 14 7 Usage Notes on the Multi functional Timer 14 8 Sample Programs for the Multi functional Timer ...

Page 299: ...into which data is written for transfer to the compare clear register When the timer is stopped transfer occurs immediately when the data is written to the buffer When the timer is operation data transfer from the buffer occurs when the timer value is detected to be zero Reset software clear compare match with compare clear register in up count mode will reset the counter value to 0000H The output...

Page 300: ...il of 16 bit PPG timer 0 is described in Chapter 13 Waveform Generator The waveform generator consists of three 16 bit timer registers three timer control registers and 16 bit waveform control register With waveform generator it is possible to generate real time output 16 bit PPG waveform output non overlap 3 phase waveform output for inverter control and DC chopper waveform output It is possible ...

Page 301: ...0 to RT5 Output compare 0 Output compare 1 Output compare 2 Output compare 3 Output compare 4 Output compare 5 Waveform generator RTO0 RTO1 RTO2 RTO3 RTO4 RTO5 DTTI Interrupt 29 Interrupt 31 Interrupt 34 A D trigger EXCK Interrupt 33 Interrupt 35 IN0 IN1 IN2 IN3 Pin P30 RTO0 U Pin P31 RTO1 X Pin P32 RTO2 V Pin P33 RTO3 Y Pin P34 RTO4 W Pin P35 RTO5 Z Pin P10 INT0 DTTI0 16 bit timer 0 1 2 underflow...

Page 302: ... bit compare clear buffer register Compare circuit Zero detect circuit timer clear register Mask circuit MSI2 MSI1 MSI0 ICLR ICRE IRQZF IRQZE STOP UP UP DOWN CLR CK transfer φ F 2 MC 16LX bus To input capture output compare Interrupt 34 22H A D trigger Interrupt 31 1FH Selector I0 I1 O Selector I0 I1 O Selector I0 I1 O Selector I0 I1 O Zero detect to output compare Compare clear match to output co...

Page 303: ...OP1 IOP0 IOE1 IOE0 Interrupt 12 17 21 15 19 23 generator generator Count value from free run timer Waveform Waveform Compare buffer register 0 2 4 BUF0 BTS0 Zero detect from Compare clear match from free run timer F 2 MC 16LX bus Selector I0 I1 O transfer Compare buffer register 1 3 5 transfer BUF1 BTS1 Selector I0 I1 O free run timer EG11 EG10 EG01 EG00 IEI1 IEI0 ICP0 ICP1 ICE0 ICE1 Capture regis...

Page 304: ...it Selector Dead time generator Waveform control Selector Dead time generator Waveform control Selector Dead time generator Waveform control Selector Selector Selector SIGCR DTCR2 DTCR1 TMD2 TMD1 TMD0 GTEN1 GTEN0 DTCR0 TMD2 TMD1 TMD0 GTEN1 GTEN0 TMD2 TMD1 TMD0 GTEN1 GTEN0 Output control Output control Output control RTO0 U RTO1 X RTO2 V RTO3 Y RTO4 W RTO5 Z PGEN1 PGEN0 PICSH01 RT0 RT1 RT2 RT3 RT4 ...

Page 305: ...it15 0 P24 IN0 Port 2 input output input capture 0 Not provided Set the pin as an input port DDR2 bit4 0 P25 IN1 Port 2 input output input capture 1 Set the pin as an input port DDR2 bit5 0 P26 IN2 Port 2 input output input capture 2 Set the pin as an input port DDR2 bit6 0 P27 IN3 Port 2 input output input capture 3 Set the pin as an input port DDR2 bit7 0 P30 RTO0 U Port 3 input output RTO0 CMOS...

Page 306: ...PDR read PDR write Output latch DDR read DDR write Direction latch Port data direction register DDR Pin Standby control SPL 1 Resource output Resource output enable RDR Pull up resistor Resource input About 50k Internal data bus Port data register PDR PDR read PDR write Output latch DDR read DDR write Direction latch Port data direction register DDR Pin Standby control SPL 1 Resource output Resour...

Page 307: ... 3 3 Block Diagram of P30 RTO0 to P35 RTO5 Internal data bus Port data register PDR PDR read PDR write Output latch DDR read DDR write Direction latch Port data direction register DDR Pin Standby control SPL 1 Resource output Resource output enable ...

Page 308: ...itial value Read write CL07 CL06 CL05 CL04 CL03 CL02 CL01 CL00 15 14 13 12 11 10 9 8 R W 0 Address 00005DH R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 T15 T14 T13 T12 T11 T10 T09 T08 Address 00005CH 7 6 5 4 3 2 1 0 Timer Data Register Upper Timer Data Register Lower TCDT TCDT Initial value Read write R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 Initial value Read write T07 T06 T05 T04 T03 T02 T01...

Page 309: ... 000070H ch 1 000072H ch 2 000074H ch 3 000076H ch 4 000078H ch 5 00007AH R W X R W X R W X R W X R W X R W X R W X R W X Initial value Read write OCCPB0 to OP07 OP06 OP05 OP04 OP03 OP02 OP01 OP00 15 14 13 12 11 10 9 8 Compare Control Register Upper 7 6 5 4 3 2 1 0 Compare Control Register Lower Address ch 1 00007DH ch 3 00007FH ch 5 000081H OCS1 OCS3 R W 1 R W 1 R W 0 R W 0 R W 0 R W 0 R W 0 Init...

Page 310: ... 8 Address 00006BH R 0 R 0 IEI3 IEI2 Input Capture Control Status Register 2 3 Upper ICSH23 Initial value Read write 7 6 5 4 3 2 1 0 R W 0 Address 00006AH R W 0 R W 0 R W 0 R W R W 0 R W 0 R W 0 ICP3 ICP2 ICE3 ICE2 EG31 EG30 EG21 EG20 Input Capture Control Status Register 2 3 Lower ICSL23 Initial value Read write 0 Address 000068H 7 6 5 4 3 2 1 0 Input Capture Control Register 0 1 R W 0 R W 0 R W ...

Page 311: ...TMIE TMD2 TMD1 TMD0 Address 000059H 15 14 13 12 11 10 9 8 Waveform Control Register SIGCR R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 Initial value Read write DTIE DTIF NRSL DCK2 DCK1 DCK0 NWS1 NWS0 7 6 5 4 3 2 1 0 16 bit Timer Register Lower R W X R W X R W X R W X R W X R W X R W X R W X Initial value Read write TMRR0 TMRR1 Address ch 0 000050H ch 1 000052H ch 2 000054H 15 14 13 12 11 10 9 8...

Page 312: ...ount value of the 16 bit free run timer In up count mode when this register is matched with the count value of 16 bit free run timer timer will be reset to 0000H In up down count mode when this register is matched with the count value of the 16 bit free run timer the timer changes from up count to down count and changes from down count to up count at zero detect Word access to this register is rec...

Page 313: ... the operation is stopped STOP 1 Word access instruction to the timer data register is recommended The 16 bit free run timer is initialized upon the following factors Reset Clear bit SCLR of control status register A match between compare clear register and the timer counter value in up count mode TCCSL MODE 0 15 14 13 12 11 10 9 8 R W 0 Address 00005DH R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 T1...

Page 314: ...t Read Write 0 No compare clear match Clear this bit 1 Compare clear match No effect MSI2 MSI1 MSI0 Interrupt masking selection bits 0 0 0 Interrupt is generated when 1st match 0 0 1 Interrupt is generated when 2nd match 0 1 0 Interrupt is generated when 3rd match 0 1 1 Interrupt is generated when 4th match 1 0 0 Interrupt is generated when 5th match 1 0 1 Interrupt is generated when 6th match 1 1...

Page 315: ... MSI2 to MSI0 bit13 IRQZE Zero detect interrupt request enable bit This is the interrupt request enable bit for the zero detect When this bit is 1 and the interrupt flag bit14 IRQZF is set to 1 an interrupt request will be generated to CPU bit12 to bit10 MSI2 to MSI0 Interrupt mask selection bits These bits are used to set the number of times of masking the compare clear interrupt in up count mode...

Page 316: ...µs 0 5 µs 2 µs 0 1 0 φ 4 0 25 µs 0 5 µs 1 µs 4 µs 0 1 1 φ 8 0 5 µs 1 µs 2 µs 8 µs 1 0 0 φ 16 1 µs 2 µs 4 µs 16 µs 1 0 1 φ 32 2 µs 4 µs 8 µs 32 µs 1 1 0 φ 64 4 µs 8 µs 16 µs 64 µs 1 1 1 φ 128 8 µs 16 µs 32 µs 128 µs φ Machine cycle SCLR Timer clear bit Write Read 0 Clear SCLR bit Always read as 0 1 Initialize counter to 0000H MODE Timer counting mode 0 up count mode 1 up down count mode STOP Timer ...

Page 317: ...up counting The timer will reverse its counting direction whenever the timer value matches with compare clear register This bit can be written at any time whether the timer is operating or stopped The value written to this bit is buffered and the count mode will be changed when timer value is 0000H Note Because the timer will reverse its counting direction when compare match is detected in up down...

Page 318: ...er is transferred to output compare register immediately When buffer function is enabled OCS0 OCS2 OCS4 BUF0 BUF1 0 value is transferred at compare clear match or zero detection depending on transfer selection bit BTS in compare control register OCS1 OCS3 OCS5 Word access to this register is recommended 15 14 13 12 11 10 9 8 Output Compare Buffer Register Upper 7 6 5 4 3 2 1 0 Output Compare Buffe...

Page 319: ...t compare interrupt flag OCS0 OCS2 OCS4 IOP0 IOP1 If output level is set OCS1 OCS3 OCS5 OTD0 OTD1 the output level of RT0 to RT5 corresponding to the output compare register OCCP0 to OCCP5 can be reversed Word access to this register is recommended 15 14 13 12 11 10 9 8 Output Compare Register Upper 7 6 5 4 3 2 1 0 Output Compare Register Lower Address ch 0 000071H ch 1 000073H ch 2 000075H ch 3 0...

Page 320: ... RT1 RT3 RT5 Current output value of RT1 RT3 RT5 1 Output 1 for RT1 RT3 RT5 OTE0 Output enable bit 0 General purpose port P30 P32 P34 1 Output compare output pin RTO0 RTO2 RTO4 OTE1 Output enable bit 0 General purpose port P31 P33 P35 1 Output compare output pin RTO1 RTO3 RTO5 CMOD Output level reverse mode bit 0 RT0 RT2 RT4 The level is reversed upon a match with compare register 0 2 4 RT1 RT3 RT...

Page 321: ...versed as same as when CMOD 0 However the output level of the pin RT1 RT3 RT5 corresponding to compare register 1 3 5 is reversed when a match is detected in compare register 0 2 4 or 1 3 5 If compare registers 0 2 4 and 1 3 5 have the same value the same operation as when only one compare register is used RT0 RT2 RT4 The level is reversed upon a match between the 16 bit free run timer and compare...

Page 322: ...ffer for compare register 0 2 4 BUF1 Compare buffer disable bit 0 Enable compare buffer for compare register 1 3 5 1 Disable compare buffer for compare register 1 3 5 IOE0 Compare match interrupt enable bit 0 Disable compare match interrupt for compare register 0 2 4 1 Enable compare match interrupt for compare register 0 2 4 IOE1 Compare match interrupt enable bit 0 Disable compare match interrup...

Page 323: ...re interrupt occurs when an interrupt flag IOP1 is set bit4 IOE0 Compare match interrupt enable bit This bit is used to enable output compare interrupt for compare register 0 2 4 While the 1 is written to this bit an output compare interrupt occurs when an interrupt flag IOP0 is set bit3 BUF1 Compare buffer disable bit This bit is used to disable buffer function for output compare register 1 3 5 W...

Page 324: ...onding external pin input waveform is detected Word access instruction to this register is recommended No data can be written to this register 15 14 13 12 11 10 9 8 Input Capture Data Register Upper 7 6 5 4 3 2 1 0 Input Capture Data Register Lower Address ch 0 000061H ch 1 000063H ch 2 000065H ch 3 000067H X X X X X X X X Initial value Read write CP15 CP14 CP13 CP12 CP11 CP10 CP09 CP08 Address ch...

Page 325: ...only Not used Initial value Table 14 4 5 Input Capture Control Status Register ICSH23 Bit name Function bit15 to bit10 Unused bit The read value is indeterminate Writing to this bit has no effect on the operation bit9 IEI3 Valid edge indication bit This bit is an valid edge indication bit for capture register 3 to indicate a rising or falling edge is detected 0 is written to this bit when falling ...

Page 326: ... Edge selection bit input capture 3 0 0 No edge detection stop 0 1 Rising edge detection 1 0 Falling edge detection 1 1 Both edges detection ICE2 Interrupt request enable bit input capture 2 0 Disable interrupt request 1 Enable interrupt request ICE3 Interrupt request enable bit input capture 3 0 Disable interrupt request 1 Enable interrupt request ICP2 Interrupt request flag bit input capture 2 R...

Page 327: ...e Writing 0 will clear this bit Writing 1 has no effect In read modify write operation 1 is always read bit5 ICE3 Interrupt request enable bit Input capture 3 This bit is used to enable input capture interrupt request for input capture 3 While 1 is written to this bit an input capture interrupt is generated when the interrupt flag ICP3 is set bit4 ICE2 Interrupt request enable bit Input capture 2 ...

Page 328: ...ndication bit input capture 1 0 Falling edge detected 1 Rising edge detected PGEN0 PPG output enable bit 0 Disable PPG0 output to RTO0 1 Enable PPG0 output to RTO0 PGEN1 PPG output enable bit 0 Disable PPG0 output to RTO1 1 Enable PPG0 output to RTO1 PGEN2 PPG output enable bit 0 Disable PPG0 output to RTO2 1 Enable PPG0 output to RTO2 PGEN3 PPG output enable bit 0 Disable PPG0 output to RTO3 1 En...

Page 329: ...a rising or falling edge is detected 0 is written to this bit when falling edge is detected 1 is written to this bit when rising edge is detected This bit is read only Note The read value is meaningless when EG11 EG10 00B bit8 IEI0 Valid edge indication bit This bit is an value edge indication bit for capture register 0 to indicate a rising or falling edge is detected 0 is written to this bit when...

Page 330: ...1 EG10 Edge selection bit input capture 1 0 0 No edge detection stop 0 1 Rising edge detection 1 0 Falling edge detection 1 1 Both edges detection ICE0 Interrupt request enable bit input capture 0 0 Disable interrupt request 1 Enable interrupt request ICE1 Interrupt request enable bit input capture 1 0 Disable interrupt request 1 Enable interrupt request ICP0 Interrupt request flag bit input captu...

Page 331: ...edge Writing 0 will clear this bit Writing 1 has no effect In read modify write operation 1 is always read bit5 ICE1 Interrupt request enable bit Input capture 1 This bit is used to enable input capture interrupt request for input capture 1 While 1 is written to this bit an input capture interrupt is generated when the interrupt flag ICP1 is set bit4 ICE0 Interrupt request enable bit Input capture...

Page 332: ...p time set value 1 selected clock Notes The value of 0000H cannot be set The maximum offset of non overlap time is 1 selected clock In timer mode these registers are used to set the GATE time for PPG timer 0 operation GATE time set value 1 selected clock Notes The value of 0000H cannot be set and maximum offset is 1 selected clock The maximum offset of GATE time is 1 selected clock 16 bit Timer Re...

Page 333: ...t timer to start PPG timer 0 output pulse until the 16 bit timer stopped Timer mode 1 0 0 Generate non overlap signal by RT signal Dead time timer mode 1 1 1 Generate non overlap signal by PPG timer 0 Dead time timer mode Others Prohibited TMIE Interrupt request enable bit 0 Disable an interrupt when the 16 bit timer underflow 1 Enable an interrupt when the 16 bit timer underflow TMIF Interrupt re...

Page 334: ...kes the higher priority to clear this bit bit3 TMIE Interrupt request enable software trigger bit This bit is used as the software trigger bit and interrupt enable bit for the 16 bit timer 0 2 When TMD22 to TMD0 000B or 001B this bit is used as software trigger for 16 bit timer Setting this bit from 0 to 1 trigger the 16 bit timer to reload and starts down counting When this bit is 1 and the inter...

Page 335: ... Dead time timer mode 1 1 1 Generate non overlap signal by PPG timer 0 Dead time timer mode Others Prohibited TMIE Interrupt request enable bit 0 Disable an interrupt when the 16 bit timer underflow 1 Enable an interrupt when the 16 bit timer underflow TMIF Interrupt request flag bit Read Write 0 No counter underflow detected Clear this bit 1 Counter underflow detected No effect GTEN0 GATE signal ...

Page 336: ...flow occurs simultaneously software clear takes the higher priority to clear this bit bit11 TMIE Interrupt request enable bit This bit is used as the software trigger bit and interrupt enable bit for the 16 bit timer When TMD2 to TMD0 000B or 001B this bit is used as software trigger for 16 bit timer Setting this bit from 0 to 1 trigger the 16 bit timer to reload and starts down counting When this...

Page 337: ...ise 0 1 Cancel 8 cycle noise 1 0 Cancel 16 cycle noise 1 1 Cancel 32 cycle noise DCK2 DCK1 DCK0 Operating clock selection bit 0 0 0 φ 62 5 ns φ 16 MHz 0 0 1 φ 2 125 ns φ 16 MHz 0 1 0 φ 4 250 ns φ 16 MHz 0 1 1 φ 8 500 ns φ 16 MHz 1 0 0 φ 16 1 µs φ 16 MHz 1 0 1 φ 32 2 µs φ 16 MHz 1 1 0 φ 64 4 µs φ 16 MHz 1 1 1 Prohibited φ Machine clock NRSL Noise cancellation function enable bit 0 DTTI0 input does ...

Page 338: ...s simultaneously software clear takes the higher priority to clear this bit bit13 NRSL Noise cancellation function enable bit This bit is used to enable the noise cancellation function Noise cancellation circuit will receive DTTI0 input signal when the low level is held until the counter overflows The counter is n bit counter which is operated by the low level input The value of n can be 2 3 4 and...

Page 339: ...interrupt controller 16 bit Free run Timer Interrupts and EI2 OS Table 14 5 2 lists the 16 bit free run timer interrupts and EI2OS Table 14 5 1 Interrupt Control Bits and Interrupt Causes of the 16 bit Free run Timer 16 bit free run timer Compare Clear Zero Detect Interrupt request flag bit TCCSH ICLR TCCSH IRQZF Interrupt request enable bit TCCSH ICRE TCCSH IRQZE Interrupt cause 16 bit free run t...

Page 340: ...register OCCP4 OCCP5 Table 14 5 4 16 bit Output Compare Interrupts and EI2OS Channel Interrupt number Interrupt control register Vector table address EI2 OS Register name Address Lower Middle Upper Output compare 0 match 1 12 0CH ICR00 0000B0H FFFFCCH FFFFCDH FFFFCEH O Output compare 1 match 2 15 0FH ICR02 0000B2H FFFFC0H FFFFC1H FFFFC2H Output compare 2 match 3 17 11H ICR03 0000B3H FFFFB8H FFFFB9...

Page 341: ...le 14 5 5 Interrupt Control Bits and Interrupt Causes of the 16 bit Input Capture 0 to 3 16 bit input capture 0 1 16 bit input capture 2 3 Interrupt request flag bit PICSL01 ICP0 ICP1 ICSL23 ICP2 ICP3 Interrupt request enable bit PICSL01 ICE0 ICE1 ICSL23 ICE2 ICE3 Interrupt cause Valid edge is detected in IN0 IN1 Valid edge is detected in IN2 IN3 Table 14 5 6 16 bit Input Capture Interrupts and EI...

Page 342: ... timer compare clear uses EI2OS interrupts of 16 bit input capture channels 0 1 must be disabled Table 14 5 8 Waveform Generator Interrupts and EI2OS Channel Interrupt number Interrupt control register Vector table address EI2OS Register name Address Lower Middle Upper 16 bit timer 0 1 2 underflow 1 29 1DH ICR09 0000B9H FFFF88H FFFF89H FFFF8AH DTTI0 2 20 14H ICR04 0000B4H FFFFACH FFFFADH FFFFAEH 1...

Page 343: ...t compare The 16 bit output compare is used to compare the value set in the specified output compare register with the value of the 16 bit free run timer If a match is detected the interrupt flag is set and the output level is inverted 16 bit input capture The 16 bit input capture is used to detect a specified valid edge If a valid edge is detected the interrupt flag is set and the value of 16 bit...

Page 344: ... 1 is written to the SCLR bit of the TCCSL register during operation The timer will be cleared at the valid edge of count clock Note If writing 0 to the SCLR bit before a valid edge of count clock the SCLR bit is cleared and the timer would not be cleared to 0000H When 0000H is written to the TCDT register during stop Reset By a reset the counter is immediately cleared By a software clear or a mat...

Page 345: ... TCDT counts up until counter value matches value of compare clear register CPCLR then counter changes from up count to down count counts down until counter value reaches 0000H and then counts up again There is a buffer in mode bit TCCSL MODE it can be written at any time no matter the timer is operating or stopped While the timer is operating value written to this bit is buffered and the count mo...

Page 346: ...LR Figure 14 6 3 Operation in Up count Mode with Compare Clear Buffer is disabled TCCSL BFE 0 Figure 14 6 4 Operation in Up count Mode with Compare Clear Buffer is enabled TCCSL BFE 1 FFFFH BFFFH 7FFFH 3FFFH 0000H BFFFH Counter value Time Reset Timer starts Zero detect BFFFH Compare clear buffer register value Compare clear register value 7FFFH FFFFH FFFFH 7FFFH Zero detect FFFFH BFFFH 7FFFH 3FFFH...

Page 347: ... Up down Count Mode with Compare Clear Buffer enabled TCCSL BFE 1 FFFFH BFFFH 7FFFH 3FFFH 0000H BFFFH Counter value Time Reset Compare clear Zero detect buffer register Timer starts Compare clear match BFFFH value Compare clear register value 7FFFH 7FFFH FFFFH FFFFH ...

Page 348: ...ear register CPCLR Zero detect interrupt is generated when the timer value reaches 0000H Note Software clear TCCSL SCLR 1 will not generate zero detect interrupt Figure 14 6 6 Interrupts Generated in Up count Mode TCCSL MODE 0 Figure 14 6 7 Interrupts Generated in Up down Count Mode TCCSL MODE 1 N 1 N 0 1 Compare clear interrupt Counter value Zero detect interrupt N N 1 0 Compare clear interrupt C...

Page 349: ...ode TCCSL MODE In up count mode only compare clear interrupt can be masked zero detect interrupt is generated in every zero detection In up down count mode only zero detect interrupt can be masked compare clear interrupt is generated in every compare clear Note Software clear TCCSL SCLR 1 will not generate zero detection Figure 14 6 8 Compare Clear Interrupt masked in Up count Mode FFFFH BFFFH 7FF...

Page 350: ...falling edge when initial value of external clock input is 0 after external clock mode is selected TCCSH ECKE 1 Figure 14 6 10 16 bit Free run Timer Count Timing FFFFH BFFFH 7FFFH 3FFFH 0000H Counter value Time Reset Timer starts Zero detect 1st 2nd 3rd 4th Compare clear interrupt Zero detect interrupt Software clear Compare clear match 1st 2nd 3rd 4th 5th 6th 5th 6th Both zero detect interrupt an...

Page 351: ...nd the output level is inverted 16 bit Output Compare Operation Compare operation can be performed for individual channel OCS1 OCS3 OCS5 CMOD 0 Figure 14 6 11 Sample Output Waveform when Compare Registers 0 and 1 are used individually when the Initial Output Value is 0 Free run Timer in Up count Mode FFFFH BFFFH 7FFFH 3FFFH 0000H RT0 RT1 BFFFH 7FFFH Counter value Time Reset Compare register 0 Comp...

Page 352: ...tput Waveform when Compare Registers 0 and 1 are used in a Pair when the Initial Output Value is 0 Free run Timer in Up count Mode FFFFH BFFFH 7FFFH 3FFFH 0000H RT0 RT1 BFFFH 7FFFH Counter value Time Reset Compare register 0 Compare register 1 Compare 0 Compare 1 value value interrupt interrupt FFFFH BFFFH 7FFFH 3FFFH 0000H RT0 RT1 BFFFH 7FFFH Counter value Time Reset Compare register 0 Compare re...

Page 353: ...pare Buffer is disabled Free run Timer in Up count Mode FFFFH BFFFH 7FFFH 3FFFH 0000H RT0 RT1 BFFFH 7FFFH Counter value Time Reset Compare register 0 Compare register 1 Compare 0 Compare 1 value value interrupt interrupt associated with compare 0 associated with compare 0 1 FFFFH BFFFH 7FFFH 3FFFH 0000H BFFFH Counter value Time Reset Interrupt Compare clear match Timer starts Compare clear match B...

Page 354: ... 14 6 16 Sample Output Waveform when Compare Buffer is enable Free run Timer in Up down Count Mode FFFFH BFFFH 7FFFH 3FFFH 0000H 3FFFH Counter value Time Reset Interrupt Zero detection Timer starts Compare clear match Compare buffer Compare register 0 value 3FFFH 3FFFH BFFFH BFFFH register 0 value RT0 BFFFH BFFFH ...

Page 355: ... register is updated comparison with the counter value is not performed Figure 14 6 17 Compare Operation upon Update of Compare Registers Figure 14 6 18 Compare Interrupt Timing Figure 14 6 19 Output Pin Change Timing N M N 1 N 2 N 3 L N 1 N 3 Counter value Compare Compare 0 stop Compare 1 stop Compare register 0 value register 0 write Compare Compare register 1 value register 1 write No match sig...

Page 356: ...Input Capture Operation Figure 14 6 20 Sample Input Capture Timing FFFFH BFFFH 7FFFH 3FFFH 0000H IN1 IN0 3FFFH BFFFH 3FFFH 7FFFH Counter value Reset Capture register 0 Capture register 1 Capture register Capture 0 interrupt Capture 1 interrupt Capture example example IN example Undefined Undefined Undefined Note Capture 0 Rising edge Capture 1 Falling edge Capture example Both edges Interrupt is g...

Page 357: ...UNCTIONAL TIMER 16 bit Input Capture Input Timing Figure 14 6 21 16 bit Input Capture Timing for Input Signals N N 1 N 1 Counter value Input capture Capture signal Capture register Interrupt Valid edge input Machine clock φ ...

Page 358: ...rflow x 0 1 Always 0 PPG0 output pulse from rising edge of RTx to 16 bit timer 1 underflow x 2 3 PPG0 output pulse from rising edge of RTx to 16 bit timer 2 underflow x 4 5 0 1 0 1 1 Gate triggered PPG0 output pulse from rising edge of RTx to 16 bit timer 0 underflow x 0 1 OR output H from RTx y z rising edge to timer 0 1 2 underflow x 0 1 y 2 3 z 4 5 Gate triggered PPG0 output pulse from rising e...

Page 359: ...RT3 RT5 is operated with one 16 bit timer 0 1 2 to generate six individual gate signal And these six gate signals are logically OR to generate a GATE signal to trigger PPG0 counting If PGEN0 to PGEN5 signal is also used six different waveforms can be output to RTO0 to RTO5 by using one PPG0 only Generating GATE Signal during Each RTx is at H Level when GTENx is active DTCR0 DTCR1 DTCR2 TMD2 to TMD...

Page 360: ...e 16 bit timer 0 is used for RT0 and RT1 16 bit timer 1 is used for RT2 and RT3 16 bit timer 2 is used for RT4 and RT5 Therefore do not use an RT and attempt to start the corresponding timer that is already operating Doing so may cause that the outputting GATE signal will be extended and malfunction will be occurred Count value FFFFH BFFFH 3FFFH 0000H 7FFFH Time BFFFH 7FFFH Compare register 0 valu...

Page 361: ...re do not use an RT and attempt to start PPG0 which is under operation Doing so may cause that the outputting GATE signal will be extended and malfunction will be occurred Setting up registers TCDT 0000H TCCS XXXXXXXXXX0X0XXXB CPCLR XXXXH Cycle setting OCCP0 to OCCP5 XXXXH Compare value OCS0 to OCS5 XX0XXXXXXXXXX11B DTCR0 to DTCR2 011XX010B TMRR0 to TMRR2 XXXXH Non overlap timing setting SIGCR XXX...

Page 362: ...down counting from TMRR0 TMRR1 TMRR2 value at the next RT s edge Figure 14 6 25 Non overlap Signal Generation by RT1 RT3 RT5 in Normal Polarity Setting up registers TCDT 0000H TCCS X XXXXXX0X0XXXB OCCP0 to OCCP5 XXXXH Compare value TMRR0 to TMRR2 XXXXH Non overlap timing setting SIGCR XXXXXXXXB DTTI0 input and 16 bit timer count clock setting Note X must be set according to the operation CPCLR XXX...

Page 363: ...by RT1 RT3 RT5 in Inverted Polarity Setting up registers TCDT 0000H TCCS XXXXXXXXXX0X0XXXB OCCP0 to OCCP5 XXXXH Compare value TMRR0 to MRR2 XXXXH Non overlap timing setting SIGCR XXXXXXXXB DTTI0 input and 16 bit timer count clock setting Note X must be set according to the operation Count value RT1 RTO0 U RTO1 X 1 machine cycle 1 5 machine cycle TMRR0 set value Pin name Output signal RTO0 U Invert...

Page 364: ...ormal Polarity Pin name Output signal RTO0 U Signal with delay is applied at PPG0 rising edge RTO2 V Signal with delay is applied at PPG0 rising edge RTO4 W Signal with delay is applied at PPG0 rising edge RTO1 X Inverted signal with delay is applied at PPG0 falling edge RTO3 Y Inverted signal with delay is applied at PPG0 falling edge RTO5 Z Inverted signal with delay is applied at PPG0 falling e...

Page 365: ...n Inverted Polarity Setting up registers TCDT 0000H TCCS XXXXXXXXXX0X0XXXB CPCLR XXXXH Cycle setting OCCP0 to OCCP5 XXXXH Compare value OCS0 to OCS5 XX1XXXXXXXXXX11B DTCR0 to DTCR2 1XXXX111B TMRR0 to TMRR2 XXXXH Non overlap timing setting SIGCR XXXXXXXXB DTTI0 input and 16 bit timer count clock setting Note X must be set according to the operation Count value PPG0 RTO0 U RTO1 X 1 machine cycle 1 5...

Page 366: ... running for the waveform generator operation but no waveform will outputted to external pins P30 RTO0 to P35 RTO5 Figure 14 6 29 Operation when DTTI0 Input is enabled Setting up registers TCDT 0000H TCCS XXXXXXXXXX0X0XXXB OCCP0 to OCCP5 XXXXH Compare value PDR3 XXXXXX00B Inactive level setting TMRR0 to TMRR2 XXXXH Non overlap timing setting SIGCR 1XXXXXXXB DTTI0 input and 16 bit timer count clock...

Page 367: ...it uses a peripheral clock input is invalidated even if the DTTI0 input is enabled in a mode such as STOP mode in which the oscillation stops DTTI0 Interrupt When low level of DTTI0 is detected DTTI0 interrupt flag SIGCR DTIF is set to 1 after noise cancellation time is passed and an interrupt request is sent to interrupt controller Figure 14 6 30 DTTI0 Interrupt Timing Notes If SIGCR NWS1 NWS0 is...

Page 368: ...g Always clear the IRQZF bit When the ICLR bit of the timer control status register TCCSH is set to 1 and an interrupt request is enabled TCCSH ICRE 1 control cannot be returned from interrupt processing Always clear the ICLR bit Since the 16 bit free run timer shares an interrupt vector with other resource interrupt causes must be checked carefully by the interrupt processing routine when interru...

Page 369: ...g edge of RT when TMD2 to TMD0 010B rising falling edge of RT when TMD2 to TMD0 100B or rising falling edge of PPG0 when TMD2 to TMD0 111B For example changing TMD2 to TMD0 from 100B to 111B you can set in following procedures 1 set TMRR0 TMRR1 TMRR2 to a very small value like 0001H 2 set RT1 RT3 RT5 to output L H and wait until timer 0 1 2 underflow 3 change mode bits TMD2 TMD1 and TMD0 and corre...

Page 370: ...er for the 16 bit free run timer TCCS EQU 00005EH Timer control status register CPCLRB EQU 000058H Compare clear buffer register ICLR EQU TCCS 9 Interrupt request flag bit Main program CODE CSEG START Assumes that stack pointer SP has already been initialized AND CCR 0BFH Interrupt disable MOV I ICR11 00H Interrupt level 0 strongest MOVW I CPCLRB 0FFFFH Set compare clear value to change 16 bit fre...

Page 371: ... timer is matched with output compare 0 The 16 bit free run timer is used in up count mode EI2OS is not used 16 MHz is used for the machine clock and 62 5 ns is used for the count clock of 16 bit free run timer Coding example ICR00 EQU 0000B0H Interrupt control register for the output compare 0 TCCS EQU 00005EH Timer control status register CPCLRB EQU 000058H Compare clear buffer register OCCP0 EQ...

Page 372: ...output compare output Enables compare match interrupt 0 Clears interrupt flag and enable output compare MOV ILM 07H Sets ILM in PS to level 7 OR CCR 40H Interrupt enable LOOP MOV A 00H Endless loop MOV A 01H BRA LOOP Interrupt program WARI CLRB I IOP Clears interrupt request flag User processing RETI Returns from interrupt CODE ENDS Vector setting VECT CSEG ABS 0FFH ORG 0FFCCH Sets vector for inte...

Page 373: ...354 CHAPTER 14 MULTI FUNCTIONAL TIMER ...

Page 374: ...1 Overview of Multi pulse Generator 15 2 Block Diagram of Multi pulse Generator 15 3 Multi pulse Generator Pins 15 4 Registers of Multi pulse Generator 15 5 Multi pulse Generator Interrupts 15 6 Operation of Multi pulse Generator 15 7 Usage Notes on the Multi pulse Generator 15 8 Sample Programs for the Multi pulse Generator ...

Page 375: ...load timer is underflow or when the OPDBR0 register is written one of Output Data Buffer Registers OPDBRB to OPDBR0 will be loaded into the Output Data Register OPDR The Output Data Register OPDR determines the 16 bit PPG timer output to which OPT output OPT5 to OPT0 By loading different Output Data Buffer Registers OPDBRB to OPDBR0 into the Output Data Register OPDR Various combination of OPT out...

Page 376: ...ing sequencer state changes the write timing WTO needs to be delayed and synchronized with the next coming edge of PPG output waveform See Figure 15 1 1 and Figure 15 1 2 for details This function can be enabled or disabled by software WTS1 and WTS0 bits of the Input Control Register IPCR are used to disable this function and to select the polarity of the PPG edge to synchronize with Figure 15 1 1...

Page 377: ...put and Table 15 1 2 shows the noise width for noise filter of SNI2 to SNI0 pins The followings are conditions for the input position detect circuit 3 edge selection for all SNI2 to SNI0 Rising edge falling edge and both edges Compare the levels of SNI2 to SNI0 inputs with RDA2 to RDA0 bits of Output Data Register OPDR RDA2 to RDA0 After above condition met the writing timing signal will be genera...

Page 378: ...detail of 16 bit Reload Timer 0 is described in Chapter 12 16 bit Reload Timer Waveform Sequencer The Waveform Sequencer is the heart of Multi pulse Generator that can generate various waveforms The block diagram is shown in Figure 15 2 2 WAVEFORM P05 OPT5 P04 OPT4 P03 OPT3 P01 OPT1 P02 OPT2 P00 OPT0 16 BIT PPG TIMER 1 P12 INT2 DTTI1 P44 SNI1 P45 SNI2 P43 SNI0 16 BIT RELOAD TIMER 0 SEQUENCER SNI1 ...

Page 379: ...ROL CIRCUIT Pin Pin Pin Pin Pin Pin DTTI1 Control Circuit Noise Filter OPCR Register DTIE DTIF NRSL OPS2 OPS1 OPS0 WTIF WTIE PDIF PDIE OPE5 OPE4 OPE3 OPE2 OPE1 OPE0 CONTROL UNIT COMPARISON CIRCUIT Pin IPCR Register WTS1 WTS0 CPIF CPIE CPD2 CPD1 CPD0 CMPE CPE1 CPE0 SNC2 SNC1 SNC0 SEE2 SEE1 SEE0 SYN Circuit WTS1 WTS0 OPS1 OPS0 OPS2 P44 SNI1 Pin P45 SNI2 Pin WRITE TIMING INTERRUPT COMPARE MATCH INTER...

Page 380: ... the bit15 to bit12 of Output Data Register OPDR BNKF RDA2 to RDA0 to select which Output Data Buffer Register OPDBRB to OPDBR0 is loaded into Output Data Register DTTI1 Control The DTTI1 Control is used to stop the Multi pulse Generator output in case of emergency that is triggered by level 0 of DTTI1 input Noise Filter The Noise Filter is used to filter out the noise of the input signal in which...

Page 381: ...e OPT5 to OPT0 and DTTI1 pins Output Data Buffer Register OPDBRB to OPDBR0 The Output Data Buffer Register is composed of twelve registers OPDBRB to OPDBR0 The value of the OPDBRx register specified by the BNKF RDA2 to RDA0 bits is loaded into the OPDR register at the rising edge of the write signal generated by the Data Write Control Unit Output Data Register OPDR The Output Data Register OPDR is...

Page 382: ... used to compare the count value of the 16 bit Up Counter and the Compare Clear register Compare Clear Register CPCR The Compare Clear Register CPCR is used to store the 16 bit value which is used to compare the value of the 16 bit Up Counter 16 bit up counter Prescaler TCLR ICLR ICRE MODE TMEN CLK2 CLK1 CLK0 Compare Clear Interrupt CCIRT 16 bit compare clear register Compare circuit Clock 16 bit ...

Page 383: ...enable disable the interrupt Block Diagram of Data Write Control Unit Figure 15 2 4 Block Diagram of Data Write Control Unit 1 Cycle Delay Circuit The 1 Cycle Delay Circuit is used to delay one CPU clock cycle of the trigger signal when the Output Data Buffer Register 0 OPDBR0 is written 1 CYCLE TIN From 16 bit DELAY TIN0O WTIN0 WTO Write OPDBR0 SELECTOR 1 FALLING EDGE RISING AND FALLING DECODER W...

Page 384: ... Detector The Falling Edge Detector is used to detect the falling edge of the 16 bit Reload Timer 0 output TOUT Rising and Falling Edge Detector The Rising and Falling Edge Detector is used to detect the rising and falling edge of the 16 bit Reload Timer 0 output TOUT When timer underflow trigger is used in following modes the WTIN0 signal is generated by the trigger edge selected by OPS2 to OPS0 ...

Page 385: ...n input SNI2 to SNI0 with 3 different kind of edge setting If the selector is selected a data write time output signal is generated when an effective edge is detected at the one of SNI2 to SNI0 inputs Noise Filter The Noise Filter is used to filter out the noise of the input signal in which there are 4 kind of sampling clock for selection Selector The Selector is used to select from either Edge De...

Page 386: ...e OPT5 to OPT0 pin P43 SNI0 to P45 SNI2 Pins P43 SNI0 to P45 SNI2 pins can function either as a general purpose I O port P43 to P45 or as the position detect input for Multi pulse Generator Set P43 SNI0 to P45 SNI2 pins as an input port in the data direction register DDR4 bit5 to bit3 000B when using as SNI2 to SNI0 pins P12 INT2 DTTI1 Pin P12 INT2 DTTI1 pin can function either as a general purpos...

Page 387: ...er DDR Pin Standby control SPL 1 Resource output Resource output enable RDR Pull up resistor About 50kΩ Direct resource input Internal data bus Port data register PDR PDR read PDR write Output latch DDR read DDR write Direction latch Port data direction register DDR Pin Standby control SPL 1 Resource output Resource output enable RDR Pull up resistor About 50kΩ Resource input Port data register PD...

Page 388: ...ster Upper Address 00008AH Read Write Initial Value 7 6 5 4 3 2 1 0 OPCLR R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 Output Control Register Lower Address 003FF9H Read Write Initial Value 15 14 13 12 11 10 9 8 OPDR R 0 R 0 R 0 R 0 R X R X R X R X Output Data Register Upper Address 003FF8H Read Write Initial Value 7 6 5 4 3 2 1 0 OPDR R X R X R X R X R X R X R X R X Output Data Register Lower ...

Page 389: ...s Lower Address 00008DH Read Write Initial Value 15 14 13 12 11 10 9 8 IPCUR R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 Input Control Register Upper Address 00008CH Read Write Initial Value 7 6 5 4 3 2 1 0 IPCLR R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 Input Control Register Lower 003FF7H to E1H 003FF6H to E0H _ RDA0 OP51 OP50 OP41 OP40 RDA1 RDA2 OP31 OP30 OP21 OP20 OP11 OP10 OP01 OP00...

Page 390: ...FCH Read Write Initial Value 7 6 5 4 3 2 1 0 TMBR R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 Timer Buffer Register Lower 003FFBH 003FFAH _ CL12 CL11 CL10 CL09 CL08 CL13 CL14 CL07 CL06 CL05 CL04 CL03 CL02 CL01 CL00 T15 T13 T12 T11 T10 T09 T08 T07 T06 T05 T04 T03 T02 T01 T00 CL15 T14 Address 00008FH Read Write Initial Value 15 14 13 12 11 10 9 8 NCCR R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 Timer Contro...

Page 391: ...to OPDR is triggered by the16 bit reload timer 0 underflow 0 1 0 Data transfer from OPDBR to OPDR is triggered by the position detection input 0 1 1 Data transfer from OPDBR to OPDR is triggered by the write signal generated by the 16 bit reload timer 0 underflow the 16 bit timer is started by the positon detection comparison circuit 1 0 0 Data transfer from OPDBR to OPDR is triggered by the write...

Page 392: ...Therefore the pulse width of noise that can be cancelled is about 2n machine cycles Note When the noise cancellation circuit is enable the input becomes invalid in a mode such as STOP mode in which the internal clock is stopped bit12 to bit10 OPS2 to OPS0 Data transfer method selection bits OPTx pin output timing control selection bits These bits are used to select the OPDR register write timing c...

Page 393: ...2 output enable bit 0 Disable OPT2 pin output Initial value 1 Enable OPT2 pin output OPE3 OPT3 output enable bit 0 Disable OPT3 pin output Initial value 1 Enable OPT3 pin output OPE4 OPT4 output enable bit 0 Disable OPT4 pin output Initial value 1 Enable OPT4 pin output OPE5 OPT5 output enable bit 0 Disable OPT5 pin output Initial value 1 Enable OPT5 pin output PDIE Position detection interrupt en...

Page 394: ... pins this bit is set to 1 When this bit is set to 1 the interrupt is generated if the position detection interrupt enable bit PDIE is also set to 1 This bit is cleared by writing 0 Writing 1 has no effect In read modify write operation 1 is always read bit6 PDIE Position detect interrupt enable bit Position detection interrupt enable bit When this bit is set to 1 the interrupt is generated if pos...

Page 395: ...ts 0 0 Pin OPT5 outputs L level 0 1 Pin OPT5 outputs the output of the PPG timer 1 0 Pin OPT5 outputs the inverted output of the PPG timer 1 1 Pin OPT5 outputs H level BNKF RDA2 RDA1 RDA0 OPDBR register selection bits 0 0 0 0 Data in OPDBR0 is loaded to OPDR 0 0 0 1 Data in OPDBR1 is loaded to OPDR 0 0 1 0 Data in OPDBR2 is loaded to OPDR 0 0 1 1 Data in OPDBR3 is loaded to OPDR 0 1 0 0 Data in OP...

Page 396: ...the addresses of the OPDBR registers and decide which Output Data Buffer Register value is loaded into the OPDR register bit11 bit10 OP51 OP50 OPT5 output waveform selection bits These bits are used to select the kind of the output waveform to the OPT5 pin bit9 bit8 OP41 OP40 OPT4 output waveform selection bits These bits are used to select the kind of the output waveform to the OPT4 pin ...

Page 397: ...orm selection bits 0 0 Pin OPT1 outputs L level 0 1 Pin OPT1 outputs the output of the PPG timer 1 0 Pin OPT1 outputs the inverted output of the PPG timer 1 1 Pin OPT1 outputs H level OP21 OP20 OPT2 output waveform selection bits 0 0 Pin OPT2 outputs L level 0 1 Pin OPT2 outputs the output of the PPG timer 1 0 Pin OPT2 outputs the inverted output of the PPG timer 1 1 Pin OPT2 outputs H level OP31 ...

Page 398: ...orm to the OPT3 pin bit5 bit4 OP21 OP20 OPT2 output waveform selection bits These bits are used to select the kind of the output waveform to the OPT2 pin bit3 bit2 OP11 OP10 OPT1 output waveform selection bits These bits are used to select the kind of the output waveform to the OPT1 pin bit1 bit0 OP01 OP00 OPT0 output waveform selection bits These bits are used to select the kind of the output wav...

Page 399: ...etting for OPT4 pin to output H level OP51 OP50 OPT5 output waveform selection bits 0 0 Setting for OPT5 pin to output L level 0 1 Setting for OPT5 pin to output the output of the PPG timer 1 0 Setting for OPT5 pin to output the inverted output of the PPG timer 1 1 Setting for OPT5 pin to output H level BNKF RDA2 RDA1 RDA0 OPDBR register selection bits 0 0 0 0 Set OPDBR0 as next to be loaded to OP...

Page 400: ...t Data Buffer Register value is loaded into the OPDR register after it is loaded into the OPDR register bit11 bit10 OP51 OP50 OPT5 output waveform selection bits These bits are used to select the kind of the output waveform to the OPT5 pin after it is loaded into the OPDR register bit9 bit8 OP41 OP40 OPT4 output waveform selection bits These bits are used to select the kind of the output waveform ...

Page 401: ... OPT1 pin to output L level 0 1 Setting for OPT1 pin to output the output of the PPG timer 1 0 Setting for OPT1 pin to output the inverted output of the PPG timer 1 1 Setting for OPT1 pin to output H level OP21 OP20 OPT2 output waveform selection bits 0 0 Setting for OPT2 pin to output L level 0 1 Setting for OPT2 pin to output the output of the PPG timer 1 0 Setting for OPT2 pin to output the inv...

Page 402: ...0 OPT2 output waveform selection bits These bits are used to select the kind of the output waveform to the OPT2 pin after it is loaded into the OPDR register bit3 bit2 OP11 OP10 OPT1 output waveform selection bits These bits are used to select the kind of the output waveform to the OPT1 pin after it is loaded into the OPDR register bit1 bit0 OP01 OP00 OPT0 output waveform selection bits These bits...

Page 403: ... RDA2 to RDA0 000 0 0 1 Compare match if RDA2 to RDA0 001 0 1 0 Compare match if RDA2 to RDA0 010 0 1 1 Compare match if RDA2 to RDA0 011 1 0 0 Compare match if RDA2 to RDA0 100 1 0 1 Compare match if RDA2 to RDA0 101 1 1 0 Compare match if RDA2 to RDA0 110 1 1 1 Compare match if RDA2 to RDA0 111 CPIE Comparison interrupt request enable bit 0 Disable interrupt Initial value 1 Enable interrupt CPIF...

Page 404: ...terrupt enable bit CPIE is also set to 1 the interrupt is generated This bit is cleared by writing 0 Writing 1 has no effect In read modify write operation 1 is always read bit12 CPIE Comparison interrupt request enable bit Comparison interrupt enable bit When this bit is set to 1 and the comparison interrupt request flag CPIF is also set to 1 the interrupt is generated bit11 to bit9 CPD2 to CPD0 ...

Page 405: ...e SNI2 edge detection SNC0 Noise filter enable bit for SNI0 0 SNI0 input do not go through the noise cancellation circuit 1 SNI0 input goes through the noise cancellation circuit SNC1 Noise filter enable bit for SNI1 0 SNI1 input do not go through the noise cancellation circuit 1 SNI1 input goes through the noise cancellation circuit SNC2 Noise filter enable bit for SNI2 0 SNI2 input do not go thr...

Page 406: ...ion circuit starts the internal n bit counter when an active level is inputted the value of n can be 2 3 4 5 which depends on the setting of S21 S20 S11 S10 and S01 S00 bits in the Noise Cancellation Register If the active level is held until the counter overflows the circuit accepts input from the SNI2 to SNI0 pins Therefore the pulse width of noise that can be cancelled is about 2n machine cycle...

Page 407: ...nt value of 16 bit timer 16 bit timer is reset to 0000H and the compare clear interrupt flag is set Furthermore when the interrupt operation is enabled interrupt request is sent to the CPU If the Compare Clear Register CPCR is loaded a value same as the Timer Counter value at that moment the comparison operation will NOT be performed until next same counter value Figure 15 4 10 Compare Clear Regis...

Page 408: ...etection trigger is generated and the counter is then cleared to 0000H Note Word access instruction to the Timer Buffer Register must be used Figure 15 4 11 Timer Buffer Register TMBR 15 14 13 12 11 10 9 8 R 0 Address 003FFDH R 0 R 0 R 0 R 0 R 0 R 0 R 0 T15 T14 T13 T12 T11 T10 T09 T08 Address 003FFCH 7 6 5 4 3 2 1 0 Timer Buffer Register Upper Timer Buffer Register Lower TMBR TMBR Initial value Re...

Page 409: ... µs 1 µs 4 µs 0 1 1 φ 8 0 5 µs 1 µs 2 µs 8 µs 1 0 0 φ 16 1 µs 2 µs 4 µs 16 µs 1 0 1 φ 32 2 µs 4 µs 8 µs 32 µs 1 1 0 φ 64 4 µs 8 µs 16 µs 64 µs 1 1 1 φ 128 8 µs 16 µs 32 µs 128 µs φ Machine cycle TMEN Timer enable bit 0 Counting is disabled Initial value 1 Counting is enabled ICRE Compare clear interrupt request enable bit 0 Interrupt is disabled 1 Interrupt is enabled ICLR Compare clear interrupt ...

Page 410: ...ecomes 1 Interrupt is generated when the interrupt request enable bit bit12 ICRE is set to 1 Writing 0 clears this bit Writing 1 has no effect In read modify write operation 1 is always read bit4 ICRE Compare clear interrupt request enable bit This is the interrupt request enable bit for the compare clear When this bit is 1 and the interrupt flag bit13 ICLR is set to 1 an interrupt is generated bi...

Page 411: ...W D1 D0 DTTI1 noise width selection bit 0 0 Cancel 4 cycle noise 0 1 Cancel 8 cycle noise 1 0 Cancel 16 cycle noise 1 1 Cancel 32 cycle noise S01 S00 SNI0 noise width selection bit 0 0 Cancel 4 cycle noise 0 1 Cancel 8 cycle noise 1 0 Cancel 16 cycle noise 1 1 Cancel 32 cycle noise S11 S10 SNI1 noise width selection bit 0 0 Cancel 4 cycle noise 0 1 Cancel 8 cycle noise 1 0 Cancel 16 cycle noise 1 ...

Page 412: ... width to be removed for SNI2 pin bit5 bit4 S11 S10 Noise width selection bits These bits are used to specify the noise pulse width to be removed for SNI1 pin bit3 bit2 S01 S00 Noise width selection bits These bits are used to specify the noise pulse width to be removed for SNI0 pin bit1 bit0 D1 D0 Noise width selection bits These bits are used to specify the noise pulse width to be removed for DT...

Page 413: ...tch Interrupt DTTI1 Interrupt Write Timing Interrupt is multiplexed with Compare Clear Interrupt and Position Detect Interrupt is multiplexed with Compare Match Interrupt Write Timing Interrupt If the WTIE bit of the Output Control Register OPCR WTIE is set to 1 this Write Timing Interrupt is generated when the write timing is generated by the Data Write Control Circuit to make data transfer from ...

Page 414: ...e Input Control Register IPCR CPIF is set to 1 DTTI1 Interrupt If the DTIE bit of the Output Control Register OPCR DTIE is set to 1 this DTTI1 Interrupt is generated whenever a low input is detected at the DTTI1 pin When this interrupt is generated the DTTI1 interrupt flag bit of the Output Control Register OPCR DTIF is set to 1 Multi pulse Generator Interrupt Source INTERRUPT 22 This interrupt is...

Page 415: ...pt control register ICR do not use interrupts For example when Write Timing Compare Clear interrupt is used to trigger EI2 OS DTP external interrupt channels 4 5 detection must be disabled Table 15 5 1 Multi pulse Generator Interrupts and EI2 OS Interrupt cause Interrupt number Interrupt control register Vector table address EI2 OS Register name Address Lower Upper Bank DTTI1 22 16H ICR05 0000B5H ...

Page 416: ...outputs the corresponding kind of waveforms H or L or PPG output See Table 15 6 1 Output Data Register Block Diagram Figure 15 6 1 Output Data Register Block Diagram OP51 OP50 OP41 OP40 OUTPUT CONTROL CIRCUIT OPT5 OPT4 OPT3 OPT2 OPT1 OPT0 DTTI1 OP31 OP30 OP21 OP20 OP11 OP10 OP01 OP00 BNKF RDA2 RDA1 RDA0 OUTPUT DATA REGISTER 16 BIT PPG TIMER 1 DECODER DATA WRITE CONTROL UNIT POSITION DETECT CIRCUIT...

Page 417: ...by the DTTI1 pin input The OPTx output waveform timing diagram is shown in Figure 15 6 2 and the operation is explained in following paragraphs OPTx Output Waveform Timing Diagram WTS1 WTS0 00B Figure 15 6 2 OPTx Output Waveform Timing Diagram WTS1 WTS0 00B Table 15 6 1 Output Data Register OPDR OPx1 OPx0 Setting OPTx Output OPx1 OPx0 0 0 Low Level OPx1 OPx0 0 1 16 bit PPG Timer Output OPx1 OPx0 1...

Page 418: ... IPCR is set to 0 only the edge detection of SINx pins enabled by the SEE2 to SEE0 bits will engage in the edge detection operation for the position detection For instance when only the SEE0 bit is set to 1 the input edge to the pin SNI0 is in effect the data write output signal is generated only when an effective edge is detected at the SIN0 pin See Figure 15 6 3 for the timing diagram of the edg...

Page 419: ...gister Setting CMPE CPE1 CPE0 SEEx WTIN1 Output Condition 0 0 0 0 No output Initial value 0 X X 0 No output 0 0 0 1 No output 0 0 1 1 Detect SNIx rising edge 0 1 0 1 Detect SNIx falling edge 0 1 1 1 Detect SNIx both edges 1 0 0 X Prohibited 1 0 1 X Detect SNIx rising edge and SNIx RDAx comparison match 1 1 0 X Detect SNIx falling edge and SNIx RDAx comparison match 1 1 1 X Detect SNIx both edges a...

Page 420: ...input SNI2 to SNI0 16 bit Reload timer 0 acts as a delay Triggered either by the 16 bit reload timer 0 underflow or by the position detection input At the mean time the cause of generation of WTO will be defined by setting different value of OPS2 to OPS0 bit of the Output Control Register OPCR OPS2 to OPS0 Signal Flow Diagram for OPDBR0 by Setting OPS2 to OPS0 000B Figure 15 6 5 Signal Flow Diagra...

Page 421: ...mer 0 Underflow OPS2 to OPS0 001B The 16 bit reload timer 0 can be triggered by both TIN input and software to generate the write signal at this setting The write signal is controlled by the 16 bit reload timer 0 underflow OPS2 to OPS0 WTO 000 OPDBR1W RDA2 to RDA0 OPDBR0W OPDBR0 0 001 101 OP00 OPDBR1 0 OPDR POSITION 16 BIT RELOAD TIMER 0 TIN TOUT DETECTION TIN0O WTIN0 WTIN1 WTO TIN0 SNI2 to TIN0 W...

Page 422: ... OPS2 to OPS0 011B or 111B At this setting the16 bit reload timer 0 is started by the compare match or effective edge input of the position detection circuit write signal is then generated whenever the 16 bit reload timer 0 is underflow The compare match is triggered by any effective edge change in SNI2 to SNI0 pins POSITION 16 BIT RELOAD TIMER 0 TIN TOUT DETECTION TIN0O WTIN0 WTIN1 WTO TIN0 SNI2 ...

Page 423: ...r 0 is underflow The compare match is triggered by any effective edge change in SNI2 to SNI0 pins OPDR Register Write Timing Diagram OPS2 to OPS0 001B 010B 011B 100B 101B 110B 111B Figure 15 6 11 OPDR Register Write Timing Diagram OPS2 to OPS0 001B 010B 011B 100B 101B 110B 111B POSITION 16 BIT RELOAD TIMER 0 TIN TOUT DETECTION TIN0O WTIN0 WTIN1 WTO TIN0 SNI2 to TIN0 WRITE TIMING DATA WRITE CONTROL...

Page 424: ...ut waveform The output waveform is updated automatically as long as the write timing WTO is generated An example of setting the Output Data Buffer Register OPDBR is shown in Table 15 6 3 Table 15 6 3 Output Data Buffer Register OPDBR No 0 1 2 3 4 5 6 7 8 9 A BNKF 0 0 0 0 0 1 0 X X 0 1 RDA2 1 1 0 0 1 0 0 X X 1 0 RDA1 0 0 1 0 1 1 1 X X 0 1 RDA0 0 1 1 1 0 0 0 X X 0 1 OP51 0 0 0 1 0 0 0 X X 0 0 OP50 0...

Page 425: ...the Output Data Register OPDR The following sequence begins to operate according to the write timing generated No 4 No 6 No 2 No 3 No 1 No 5 No A No B No 9 No 4 and recycle The data is transferred to the Output Data Register OPDR sequentially The Output Data Buffer Register OPDBR is not used if it is not set e g No 7 and No 8 in Table 15 6 3 ...

Page 426: ...ow The value of the Output Data Buffer Register OPDBR which is selected by the BNKF RDA2 to RDA0 bits in Output Data Register OPDR is transferred to the Output Data Register OPDR when the write signal is generated from the Data Write Control Circuit However at the time when OPS2 to OPS0 000B the value of OPDBR0 is always transferred to the Output Data Register OPDR in spite of the value of BNKF RD...

Page 427: ...fer Register 0 must be used in this operation byte access to either lower register or upper register does not start any transfer operation The reload timer 0 is free to be used in this operation mode Timing Generated by OPDBR0 Write OPS2 to OPS0 000B Figure 15 6 13 Timing Generated by OPDBR0 Write OPS2 to OPS0 000B OP01 OP00 PPG OPT0 00 01 11 110 000 001 WTO RDA2 to RDA0 OPDBR2W OPDBR1W OPDBR0W OP...

Page 428: ...t reload timer 0 underflow is shown in Figure 15 6 14 and Figure 15 6 15 Timing Generated by Reload Timer Underflow Figure 15 6 14 Timing Generated by Reload Timer Underflow No 0 No 4 No 6 No 2 No 3 No 1 No 5 No A 0100 0110 0010 0011 0001 0101 1010 1011 BNKF RDA2 RDA1 OPT5 OPT4 OPT3 OPT2 OPT1 OPT0 TIMER STARTS 16 BIT RELOAD TIMER 0 UNDERFLOW OCCURS RDA0 ...

Page 429: ...thod the reload timer should be used in Reload Mode Software trigger is needed to be used for the startup of the reload timer The 16 bit reload timer 0 is needed for setting the update time in advance and executing the continuous control action Timing Generated by Reload Timer Underflow OPS2 to OPS0 001B Figure 15 6 15 Timing Generated by Reload Timer Underflow OPS2 to OPS0 001B OP01 OP00 PPG OPT0...

Page 430: ...tion Detection Figure 15 6 16 Timing Generated by Position Detection No 0 No 4 No 6 No 2 No 3 No 1 No 5 No A 0100 0110 0010 0011 0001 0101 1010 1011 BNKF RDA2 RDA1 OPT5 OPT4 OPT3 OPT2 OPT1 OPT0 SNI2 SNI1 SNI0 WRITE SIGNAL IS GENERATED WH EN TH ERE IS A COMPARISON MATCH BETWEEN RDA2 RDA0 AND SNI2 SNI1 OR ANY EFFECTI VE EDGE INPUT AT SIN2 SIN1 THE COMPARSION ISTRIGGERED BY RDA0 THE INPUT EDGE POSITI...

Page 431: ... OPDBR specified by the BNKF RDA2 to RDA0 bits is transferred to the Output Data Register OPDR and the output data is renewed automatically when pins SNI2 to SNI0 are compared with the value of the RDA2 to RDA0 bits and matches The reload timer 0 is free to be used in this operation mode Timing Generated by Position Detection OPS2 to OPS0 010B Figure 15 6 17 Timing Generated by Position Detection ...

Page 432: ... 6 18 and Figure 15 6 19 Timing Generated by Position Detection and Timer Underflow Figure 15 6 18 Timing Generated by Position Detection and Timer Underflow No 0 No 4 No 6 No 2 No 3 No 1 No 5 No A 0100 0110 0010 0011 0001 0101 1010 1011 BNKF RDA2 RDA1 OPT5 OPT4 OPT3 OPT2 OPT1 OPT0 SNI2 SNI1 SNI0 WRITE SIGNAL IS GENERATED BY 16 BIT RELOAD TI MER 0 UNDERFLOW 16 BIT RELOAD T IMER 0 DOWN COUNTI NG TI...

Page 433: ...dge input to pin SNIx is shown as in Figure 15 6 19 The 16 bit reload timer 0 is started when the pins SNI2 to SNI0 are compared with the value of the RDA2 to RDA0 bits and matches Data transfer from the Output Data Buffer register OPDBR specified by the RDA2 to RDA0 bits to the Output Data Register OPDR is triggered by the underflow of the 16 bit reload timer 0 The operation of output data is ren...

Page 434: ...nd Timer Underflow OPS2 to OPS0 011B Figure 15 6 19 Timing Generated by Position Detection and Timer Underflow OPS2 to OPS0 011B OP01 OP00 PPG OPT0 01 00 11 00 10 110 100 010 011 001 WTO RDA2 to RDA0 SNI0 SNI1 SNI2 Reload timer 0 counter action TIN0O WTIN0 TOUT TIN 11 OPDR OPDR ...

Page 435: ...n Detection or Timer Underflow Figure 15 6 20 Timing Generated by Position Detection or Timer Underflow No 0 No 4 No 6 No 2 No 3 No 1 No 5 No A 0100 0110 0010 0011 0001 0101 1010 1011 BNKF RDA2 RDA1 OPT5 OPT4 OPT3 OPT2 OPT1 OPT0 SNI2 SNI1 SNI0 RDA0 TI MER STARTS 16 BIT RELOAD TI MER 0 UNDERFLOW OCCURS WRITE SIGNAL ISGENERATED WH EN THERE IS A COMPARISON MATCH BETWEEN RDA2 RDA0 AND SNI2 SNI1 OR ANY...

Page 436: ...n or Timer Underflow OPS2 to OPS0 100B Figure 15 6 21 Timing Generated by Position Detection or Timer Underflow OPS2 to OPS0 100B 010 100 101 011 111 RDA2 to RDA0 Reload Timer 0 Counter Action WTIN0 TOUT SNI0 SNI1 SNI2 WTIN1 OP01 OP00 PPG OPT0 01 00 11 00 10 WTO 11 OPDR OPDR ...

Page 437: ... no further position detection will be recognized after the first valid detection until it is changed to ANY OTHER operation mode The OPTx output waveform is shown in Figure 15 6 22 The reload timer 0 is free to be used in this operation mode Timing Generated by One shot Position Detection OPS2 to OPS0 110B Figure 15 6 22 Timing Generated by One shot Position Detection OPS2 to OPS0 110B OP01 OP00 ...

Page 438: ...d after first valid position detection until it is changed to ANY OTHER operation mode Pin OPTx output waveform is shown as in Figure 15 6 23 In order to use this method the reload timer should be used in Single Shot Mode TIN0O must be longer than two machine cycles Timing Generated by One shot Position Detection and Timer Underflow OPS2 to OPS0 111B Figure 15 6 23 Timing Generated by One shot Pos...

Page 439: ...osition detection or timer underflow except that no further position detection will be recognized after first valid position detection until it is changed to ANY OTHER operation mode Pin OPTx output waveform is shown as in Figure 15 6 24 Timing Generated by One shot Position Detection or Timer Underflow OPS2 to OPS0 101B Figure 15 6 24 Timing Generated by One shot Position Detection or Timer Under...

Page 440: ...t the DTTI1 pin the output of OPTx is fixed at the inactive level The software can set the inactive level for each OPTX pin in PDRx of PORTx the OPTx pin is then drived by the data written in the PDRx of PORTx Even while the output is fixed at the inactive level by the input of the DTTI1 pin the timer keeps running the position detection function does not stop and the data transfer from the Output...

Page 441: ... DTTI1 Circuit Timing Diagram D1 D0 00B Note In worst case the time from DTTI1 being recognized after noise cancellation to DTISP in effect takes 2 cycles in best case it takes 1 cycle DTTI1 DTIF DTIE DTTI1 DTIF NRSL NRSL DTIE DTISP DTISP 4 Cycles φ DTIF goes to low only by writing a 0 to it ...

Page 442: ...tial value 0 1 0 DTTI1 takes effect Noise filter is not enable An L input at DTTI1 pin triggers the output of the inactive level set in PDRx The DTTI1 interrupt is generated 0 1 1 DTTI1 has no effect on OPTx 1 1 0 DTTI1 takes effect Noise filter is enable An L input at DTTI1 pin triggers the output of the inactive level set in PDRx The DTTI1 interrupt is generated 1 1 1 DTTI1 has no effect on OPTx...

Page 443: ...hich the oscillator stops SNI2 to SNI0 Pins Noise Cancellation Function When SNC2 to SNC0 bits bit5 to bit3 of the Input Control Register IPCR are set to 1 the noise cancellation function for SNI2 to SNI0 pins input can be used When the noise cancellation function is selected the input is delayed for about four machine clocks by the noise cancellation circuit Since the noise cancellation circuit u...

Page 444: ...he TCSR register during operation When a write timing signal is generated and MODE bit of the TCSR is 0 When a position detection signal is generated and MODE bit of the TCSR is 1 Reset An interrupt can be generated when the counter is cleared due to a match with Compare Clear Register There is no interrupt when an overflow occurs Note Word access to Compare Clear Register and Timer Buffer Registe...

Page 445: ... reset software clear TCLR a match with Compare Clear Register the Write Timing signal or the Position Detection signal By a reset the counter is immediately cleared By a match with Compare Clear Register software clear TCLR the Write Timing signal or the Position Detection signal the counter is cleared in synchronization with the count timing Figure 15 6 30 16 bit Timer Clear Timing N N 1 Counter...

Page 446: ...bit Timer Buffer Operation Timing Diagram Figure 15 6 31 16 bit Timer Buffer Operation Timing Diagram Timer buffer 0 or 1 CLK WTIN1 MODE WTO Load buffer 0001H 0000H Timer reset TMEN Counter value 0002H 0002H 0000H 0001H 0002H XXXXH CPU clock ...

Page 447: ... If the Compare Clear Register CPCR is loaded a value same as the Timer Counter value at that moment the comparison operation will NOT be performed until next same counter value The Compare Clear interrupt shares the same interrupt vector with the Write Timing interrupt while Compare Match interrupt shares the same vector as that of the Position Detect interrupt 16 bit Timer in Multi pulse Generat...

Page 448: ...d timer underflow transfer method OPCUR OPS2 to OPS0 010B the reload timer should be used in Reload Mode Software trigger is needed to be used for the startup of the reload timer The 16 bit reload timer is needed for setting the update time in advance and executing the continuous control action In order to use the position detection and timer underflow transfer method OPCUR OPS2 to OPS0 011B or 11...

Page 449: ...s shared resource interrupts must be disabled Usage Notes on the 16 bit Timer Notes about using a program for setting Word access to compare clear register CPCR and timer buffer register TMBR must be used Before the prescaler clock is changed the timer counter should be disable first by setting the TMEN bit to 0 Change the CLK2 CLK1 and CLK0 bits of the timer control status register TCSR only when...

Page 450: ... register for the waveform sequencer PCSR1 EQU 000042H PPG period setting register PDUT1 EQU 000044H PPG duty setting register PCNT1 EQU 000046H PPG control status register OPCR EQU 00008AH Output control register OPDBR0 EQU 003FE0H Output data buffer register WTIF EQU OPCR 9 Interrupt request flag bit Main program CODE CSEG START Assumes that stack pointer SP has already been initialized AND CCR ...

Page 451: ...LM 07H Sets ILM in PS to level 7 OR CCR 40H Interrupt enable LOOP MOV A 00H Endless loop MOV A 01H BRA LOOP Interrupt program WARI CLRB I WTIF Clears interrupt request flag User processing RETI Returns from interrupt CODE ENDS Vector setting VECT CSEG ABS 0FFH ORG 0FF94H Sets vector for interrupt 26 1AH DSL WARI ORG 0FFDCH Sets reset vector DSL START DB 00H Sets single chip mode VECT ENDS END STAR...

Page 452: ...erations of the PWC timer 16 1 Overview of the PWC Timer 16 2 Block Diagram of the PWC Timer 16 3 PWC Timer Pins 16 4 PWC Timer Registers 16 5 PWC Timer Interrupts 16 6 Operation of the PWC Timer 16 7 Usage Notes on the PWC Timer 16 8 Sample Programs for the PWC Timer ...

Page 453: ...t at the specified time interval Outputs the pulse signal that is synchronized with the timer period Selects the counter clock from three internal clocks Pulse width measurement function Measures the time between external pulse input events Selects the counter clock from three internal clocks Count mode H pulse width rising edge to falling edge L pulse width falling edge to rising edge Rising edge...

Page 454: ...ta transfer PWC read 16 16 Write enabled 16 16 Overflow Clock divider Clock 22 23 Internal clock machine clock 4 Edge detection 2 Division rate selection ERR CKS1 CKS0 Start edge selection Count end edge End edge selection Divider ON OFF Count bit output Flag setting Count start edge Count end interrupt request Overflow interrupt request 8 bit divider DIVR Overflow F F Timer clear Count enabled CK...

Page 455: ...andby control Settings required for pins P06 PWI0 Port 0 input output timer input CMOS output CMOS input Selection allowed Available Setting for the input port DDR0 bit6 0 P07 PWO0 Port 0 input output timer output Setting for timer enable PWCSL0 MOD2 to MOD0 not equal 0 P22 PWI1 Port 2 input output timer input CMOS output CMOS hysteresis input Not provided Setting for the input port DDR2 bit2 0 P2...

Page 456: ... 1 pins Figure 16 3 2 Block Diagram of the PWC Timer 1 Pins Internal data bus Port data register PDR PDR read PDR write Output latch DDR read DDR write Direction latch Port data direction register DDR Pin Standby control SPL 1 Resource output Resource output enable Resource input ...

Page 457: ...itial value Read write CKS1 CKS0 S C MOD2 MOD1 MOD0 15 14 13 12 11 10 9 8 R W X R W X R W X R W X R W X R W X R W X R W X 7 6 5 4 3 2 1 0 PWC data buffer register Upper PWC data buffer register Lower PWC0 PWC1 Initial value Read write R W X R W X R W X R W X R W X R W X R W X R W X Initial value Read write 7 6 5 4 3 2 1 0 R W 0 R W 0 DIV1 DIV0 Division rate control register Initial value Read writ...

Page 458: ...us indication Read Write 0 0 Timer stops the timer is not started or count ends No function Operation is not affected 0 1 No meaning Starts or restarts the timer enables count 1 0 No meaning Stops the timer operation disables count 1 1 Timer count operation in progress counting No function The operation is not affected ERR Error flag bit 0 Count result is not overwritten 1 Count result is overwrit...

Page 459: ...g 0 will clear the bit Writing 1 has no effect In read modify write operation 1 is always read Note In H L pulse width count mode do not use this bit for pulse width time measurement bit10 OVIE Overflow interrupt request enable bit This bit is used to enable timer overflow interrupt request When this bit is 1 and OVIR is set to 1 the overflow interrupt request will be generated to CPU Note In the ...

Page 460: ...g edge period measurement mode rising edge to rising edge 1 0 1 H pulse width measurement mode rising edge to falling edge 1 1 0 L pulse width measurement mode falling edge to rising edge 1 1 1 Falling edge to falling edge period measurement mode falling edge to falling edge S C Count mode selection Timer mode Pulse width count mode 0 Single measurement mode No reload one shot Stop after one measu...

Page 461: ...r reset the bit is initialized to 0 The bit can be read and written Note After the timer is started changing the setting is prohibited Write this bit before the timer is started or after the timer is stopped bit2 to bit0 MOD2 to MOD0 Operation mode bits Setting these bits enables selection of the operating mode and the pulse edge that fits the pulse width count After reset these bits are initializ...

Page 462: ...functions as the buffer register and contains the previous count result This register is read only Writing to this register has no effect In the single measurement mode PWCSL0 PWCSL1 S C 0 direct access to this register accesses the up count timer In this mode the register is also read only Writing to this register has no effect The register can always be read and the current timer value is read A...

Page 463: ...0 26 divided by 64 1 1 28 divided by 256 X Indeterminate R W Read and write Initial value Not used Table 16 4 3 Division Rate Control Register DIV0 DIV1 Bit name Function bit7 to bit2 Unused bit The read value is indeterminate Writing to these bits has no effect on the operation bit1 bit0 DIV1 DIV0 Division rate selection bits In the division range measurement mode this register is used to divide ...

Page 464: ...st is output to the interrupt controller PWC Timer Interrupts and EI2OS Table 16 5 2 lists the PWC timer interrupts and EI2 OS Table 16 5 1 Interrupt Control Bits and Interrupt Causes of the PWC Time PWC timer 0 PWC timer 1 Interrupt request flag bit PWCSL0 OVIR PWCSL0 EDIR PWCSL1 OVIR PWCSL1 EDIR Interrupt request enable bit PWCSL0 OVIE PWCSL0 EDIE PWCSL1 OVIE PWCSL1 EDIE Interrupt cause Overflow...

Page 465: ...th EI2 OS the counter can start EI2 OS when an overflow or measurement termination occurs However EI2OS is available only when other peripheral functions sharing the interrupt control register ICR do not use interrupts For example when PWC timer 0 uses EI2 OS interrupts of the 16 bit PPG timer 0 must be disabled ...

Page 466: ...selection of the operation in single mode or reload mode When the timer is started a timer count is performed at each count clock When an overflow occurs in the range from FFFFH to 0000H an interrupt request is issued If an overflow occurs the following occurs During single mode count is discontinued see Figure 16 6 1 During reload mode the reload register contents are reloaded to the timer and th...

Page 467: ...rminates or an overflow occurs an interrupt request can be generated When the measurement is completed the following occurs Single measurement mode The operation is discontinued see Figure 16 6 3 Continuous measurement mode The timer value is transferred to the buffer register and the timer is in free run state until the next edge is input see Figure 16 6 4 FFFFH 0000H Overflow Overflow Time Timer...

Page 468: ...ulse Timer clears Start of measurement Timer starts Timer stops EDIR flag setting termination of measurement FFFFH 0000H Time Timer count value The solid line indicates the timer count value PWC input measured pulse Timer clears Start of measurement Timer starts EDIR flag setting Data transfer to PWC Data transfer to PWC OVIR flag setting Timer starts OVIR flag setting EDIR flag setting terminatio...

Page 469: ...hot timer 0 0 0 0 Reload timer 1 0 0 0 1 Setting prohibited 0 0 0 1 Pulse width measurement Rising edge or falling edge to falling edge or rising edge All edge to edge measurement Single measurement Buffer invalid 0 0 1 0 Continuous measurement Buffer valid 1 0 1 0 Division count Divide by 4 to 256 Single measurement Buffer invalid 0 0 1 1 Continuous measurement Buffer valid 1 0 1 1 Rising edge to...

Page 470: ...ode Measurement is started after the measurement start edge is input After the measurement start edge is detected the 16 bit up count timer is cleared to 0000H and the count is started Restarting the timer While the timer operation continues after the timer is started in the timer mode or pulse width measurement mode starting the start writing 0 to the PWCSH0 PWCSH1 STRT bit is called timer restar...

Page 471: ...lues During a read operation both the STRT bit and the STOP bit have the same value However during a read operation using the read modify write instruction such as bit manipulation instruction the values of the bits are always 11B Do not use this instruction to read the values of the bits Clearing theTimer In the following cases the 16 bit up count timer is cleared to 0000H During reset When a cou...

Page 472: ...ue that is set during a count is to be changed a new reload value becomes valid when the next overflow occurs or the timer is restarted Timer Value and Reload Value In one shot operation mode direct access to PWC0 PWC1 accesses the up count timer When a value is written to PWC0 PWC1 the value is written directly to the timer When PWC0 PWC1 is read during a count operation the current timer value i...

Page 473: ...iod In timer mode when 0000H is set in PWC0 PWC1 the maximum period results Table 16 6 4 lists the count clock period and maximum timer period corresponding to the machine cycle indicated by f in the table at 16 MHz T1 65536 n1 x t T1 Time from start to stop µs n1 Timer value set in PWC0 PWC1 when the timer is started t Count clock period µs TR 65536 NR x t TR Reload period overflow period µs TPOU...

Page 474: ...e Clear interrupt flag Enable interrupt Set pulse output initial value Set value in PWC Start by STRT bit Restart Reload operation mode Single operation mode Reload PWC value to timer Start count Addition Overflow occurs Set OVIR flag Reverse POUT bit value Start count Addition Overflow occurs Set OVIR flag Reverse POUT bit value Discontinue count Discontinue operation ...

Page 475: ... to PWC0 PWC1 and the timer may continue incrementing the count in a free run state When the next count start edge is input the timer is cleared to 0000H and the pulse width count is started Notes When the count end edge is input and the timer enters a free run state the timer may overflow and the OVIR flag may be set In the H L pulse width measurement mode do not use the OVIR flag to measure the ...

Page 476: ... calculated based on the count result read from PWC0 PWC1 at the end of a count as follows Pulse Width period Measurement Range The range of the pulse width period that can be measured depends on the count clock and division rate of an input divider Table 16 6 5 lists the measurement range for the machine cycle indicated by φ at 16 MHz TW n x t Div µs TW Measured pulse width or pulse period µs n M...

Page 477: ...able 16 6 6 Measurement Mode Operation 1 2 Measurement mode MOD2 MOD1 MOD0 Measurement operation H pulse width measurement 1 0 1 The H period width is measured Start of measurement Termination of measurement When the rising edge is detected When the falling edge is detected L pulse width measurement 1 1 0 The L period width is measured Start of measurement End of measurement When the falling edge ...

Page 478: ...ode the termination edge becomes the next measurement start edge Falling edge to falling edge period measurement 1 1 1 The falling edge to falling edge time is measured Start of measurement Termination of measurement When the falling edge is detected When the falling edge is detected All edge pulse width measurement 0 1 0 The width between continuous input edges is measured Start of measurement Te...

Page 479: ...t Restart Continuous measurement mode Single operation mode Detect count start page Start count Addition Detect count end edge Set EDIR flag Clear timer Discontinue count Transfer timer value to PWC Overflow occurs Set OVIR flag Detect count start page Start count Addition Detect count end edge Set EDIR flag Clear timer Discontinue count Discontinue operation Overflow occurs Set OVIR flag Except c...

Page 480: ... stopped Setting the clock selection bits CKS1 and CKS0 of PWC control status register PWCSL0 PWCSL1 to 11B is prohibited The PWC0 PWC1 and timer values are determined when the timer is set in the one shot mode or after the operation is terminated in reload timer mode Therefore always set the values after the timer is used The PWC0 PWC1 value is undefined if the timer is set in reload timer mode a...

Page 481: ...6 MHz If a pulse width smaller than the above or a frequency larger than the above is input the timer operation is not guaranteed A noise violating the above constraint and appearing in the input signal must be reduced If a pulse width smaller than the above or a frequency larger than the above is input the timer operation is not guaranteed A noise violating the above constraint Notes about restar...

Page 482: ...n the EDIR bit of the PWC control status register PWCSH0 PWCSH1 is set to 1 and an interrupt request is enabled PWCSH0 PWCSH1 EDIE 1 control cannot be returned from interrupt processing Always clear the OVIR bit Since the PWC timer shares an interrupt vector with other resource interrupt causes must be checked carefully by the interrupt processing routine when interrupts are used Also when EI2 OS ...

Page 483: ... PWC timer PWCS0 EQU 000008H PWC control status register PWC0 EQU 00000AH PWC data buffer register OVIR EQU PWCS0 11 Interrupt request flag bit Main program CODE CSEG START Assumes that stack pointer SP has already been initialized AND CCR 0BFH Interrupt disable MOV I ICR01 00H Interrupt level 0 strongest MOVW I PSC0 0FF00H Sets the reload value MOVW I PWCS0 4409H Sets reload timer mode 0 25µ s cl...

Page 484: ...User processing RETI Returns from interrupt CODE ENDS Vector setting VECT CSEGABS 0FFH ORG 0FFC8H Sets vector for interrupt 13 0DH DSL WARI ORG 0FFDCH Sets reset vector DSL START DB 00H Sets single chip mode VECT ENDS END START ...

Page 485: ...466 CHAPTER 16 PWC Timer ...

Page 486: ...ns the functions and operation of UART 17 1 Overview of UART 17 2 Block Diagram of UART 17 3 UART Pins 17 4 UART Registers 17 5 UART Interrupts 17 6 UART Baud Rates 17 7 Operation of UART 17 8 Usage Notes on UART 17 9 Sample Program for UART ...

Page 487: ...ART Functions Function Data buffer Full duplex double buffering Transfer mode Clock synchronous Clock asynchronous start stop synchronization Baud rate A dedicated baud rate generator is provided Eight settings can be selected An external clock can be input Internal clock internal clocks supplied from 16 bit reload timer 0 can be used Data length 7 bits in asynchronous normal mode only 8 bits Sign...

Page 488: ... stop bit can be detected Table 17 1 3 UART Interrupt and EI2 OS Interrupt cause Interrupt number Interrupt control register Vector table address EI OS Register name Address Lower Upper Bank UART1 reception interrupt 37 25H ICR13 0000BDH FFFF68H FFFF69H FFFF6AH UART1 transmission interrupt 38 26H ICR13 0000BDH FFFF64H FFFF65H FFFF66H UART0 reception interrupt 39 27H ICR14 0000BEH FFFF60H FFFF61H F...

Page 489: ...smission Reception control generator circuit selection interrupt Reception bit circuit counter Reception parity counter Transmission control Transmission Transmission bit Transmission Reception status EI2 OS reception error Reception shifter circuit start circuit counter parity counter judgment circuit signal to CPU Transmission shifter Start of transmission SMR0 SMR1 SCR0 SCR1 SSR0 SSR1 Control s...

Page 490: ...er counts transmission data bits When transmission of one data item of the specified data length is complete the transmission bit counter generates a transmission interrupt request The transmission start circuit starts transmission when data is written to SODR0 SODR1 The transmission parity counter generates a parity bit for data to be transmitted when parity is enabled Reception shift register Th...

Page 491: ...le transmission Specifying whether to enable reception Status register 1 SSR0 SSR1 This register checks the transmission and reception status and error status and enables and disables transmission and reception interrupt requests Input data register 1 SIDR0 SIDR1 This register retains receive data Serial input data is converted and stored in this register Output data register 1 SODR0 SODR1 This re...

Page 492: ...t as an input port DDR4 bit0 0 P41 SOT0 Port 4 I O or serial data output Set to output enable mode SMR0 SOE 1 P42 SCK0 Port 4 I O or serial clock input output Set as an input port when a clock is input DDR4 bit2 0 Set to output enable mode when a clock is output SMR0 SCKE 1 P60 SIN1 Port 6 I O or serial data input CMOS output and CMOS hysteresis input Not provided Provided Set as an input port DDR...

Page 493: ... 17 3 1 Block Diagram of UART Pins Port data register PDR PDR read PDR write Output latch DDR read DDR write Direction latch Port data direction register DDR Pin Standby control SPL 1 Resource output Resource output enable Internal data bus Resource input ...

Page 494: ...ch 0 000021H ch 1 000025H 7 6 5 4 3 2 1 0 Serial Mode Register R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 Initial value Read write SMR0 SMR1 Address ch 0 000020H ch 1 000024H 15 14 13 12 11 10 9 8 UART Status Register SSR0 SSR1 R 0 R 0 R 0 R 0 R 1 R W 0 R W 0 R W 0 Initial value Read write PE ORE FRE RDRF TDRE BDS RIE TIE PEN P SBL CL A D REC RXE TXE MD1 MD0 CS2 CS1 CS0 RST SCKE SOE D7 D6 D5 ...

Page 495: ... 0 1 0 0 B R W Read Write Initial value RXE 0 1 REC 0 1 A D 0 1 CL 0 1 SBL 0 1 0 1 P PEN 0 1 Transmission enable bit Disables transmission Enables transmission Reception enable bit Disables reception Enables reception Reception error flag clear bit Clears the FRE ORE and PE flags Has no effect on the others Address data selection bit Data frame Address frame Data length selection bit 7 bits 8 bits...

Page 496: ...a format of a frame to be sent or received in multiprocessor mode mode 1 Select usual data when this bit is 0 and select address data when the bit is 1 bit10 REC Reception error flag clear bit This bit clears the FRE ORE and PE flags of the status register SSR Write 0 to this bit to clear the FRE ORE and PE flag Writing 1 to this bit has no effect on the others Note If UART is active and a recepti...

Page 497: ... 100B 101B 110B 111B R W Enables read and write Initial value Serial data output enable bit Uses the pin as a general I O port Uses the pin as the serial data output pin of UART Serial clock output enable bit Uses the pin as a general I O port or clock input pin of UART Uses the pin as the clock output pin of UART Clock selection bit Baud rate by dedicated baud rate generator Disables setting Baud...

Page 498: ... SCKE Serial clock output enable bit This bit controls the serial clock input output ports When this bit is 0 the P42 SCK0 and P62 SCK1 pins operate as general input output ports P42 and P62 or serial clock input pins When this bit is 1 the pins operate as serial clock output pins Note When using the P42 SCK0 and P62 SCK1 pins as serial clock input SCKE 0 pins set the P40 and P62 as input ports Al...

Page 499: ...est Enables output of transmission interrupt request Reception enable bit Disables output of reception interrupt request Enables output of reception interrupt request Transfer direction selection bit LSB first transfer from the least significant bit MSB first transfer from the most significant bit Transmission data empty flag bit Transmission data exists Writing transmission data is not allowed Tr...

Page 500: ...d to 0 when input data register SIDR0 SIDR1 is read A reception interrupt request is output when this bit and the RIE bit are 1 bit11 TDRE Transmission data empty flag bit This flag indicates the status of output data register SODR0 SODR1 This bit is cleared to 0 when transmission data is written to SODR0 SODR1 and is set to 1 when data is loaded into the transmission shift register and transmissi...

Page 501: ... When receive data is stored in this register the receive data full flag bit SSR0 SSR1 RDRF is set to 1 If a reception interrupt request is enabled at this point a reception interrupt occurs Read SIDR0 SIDR1 when the RDRF bit of the status register SSR0 SSR1 is 1 The RDRF bit is cleared automatically to 0 when SIDR0 SIDR1 is read Data in SIDR0 SIDR1 is invalid when a reception error occurs SSR0 SS...

Page 502: ...transfer to the transmission shift register is complete the bit is set to 1 When the TDRE bit is 1 the next piece of transmission data can be written If output transmission interrupt requests have been enabled a transmission interrupt is generated Write the next piece of transmission data when a transmission interrupt is generated or the TDRE bit is 1 Note SODR0 SODR1 is a write only register and ...

Page 503: ... used for the operation clocks of I O extended serial interfaces The CDCR bit configuration is shown below Figure 17 4 7 Communication Prescaler Control Register Address bit 15 14 13 12 11 10 9 8 Initial value 000019H 00001BH MD DIV2 DIV1 DIV0 0XXXX000B R W R W R W R W MD DIV2 DIV1 DIV0 div 0 Setting not allowed 1 0 0 0 1 1 0 0 1 2 1 0 1 0 3 1 0 1 1 4 1 1 0 0 5 1 1 0 1 6 1 1 1 0 7 1 1 1 1 8 MD Mac...

Page 504: ...ler When 0 is set the communication prescaler stops When 1 is set the communication prescaler operates bit14 to bit12 Reserved bits Always read as 0 bit10 to bit8 DIV2 to DIV0 Machine clock division bits These bits determines the machine clock division ratios Division ratios can only be set when MD is 1 Note If division ratio is changed wait 2 cycles as stabilization time before starting communica...

Page 505: ...of the flag bits is 1 and the reception interrupts are enabled SSR0 SSR1 RIE 1 a reception interrupt request is output to the interrupt controller When the input data register SIDR0 SIDR1 is read the receive data full flag SSR0 SSR1 RDRF is automatically cleared to 0 When 0 is written to the REC bit of the control register SCR0 SCR1 all the reception error flags SSR0 SSR1 PE ORE and FRE are cleare...

Page 506: ...on UART shares the interrupt registers ICR13 and ICR14 with the UART reception interrupts Therefore EI2OS can be started up only when no UART reception interrupts are used Table 17 5 2 UART Interrupts and EI2 OS Interrupt cause Interrupt number Interrupt control register Vector table address EI OS Register name Address Lower Upper Bank UART1 reception interrupt 37 25H ICR13 0000BDH FFFF68H FFFF69H...

Page 507: ...chronous multiprocessor mode The RDRF bit is set to 1 when a stop bit is detected If a reception error is detected the error flags ORE and FRE are set Parity errors cannot be detected Operation mode 2 synchronous normal mode The RDRF bit is set when the last bit of receive data D7 is detected If a reception error is detected the error flag ORE is set Parity and framing errors cannot be detected Fi...

Page 508: ...nterrupt request generation timing If the TDRE flag is set to 1 when a transmission interrupt is enabled SSR0 SSR1 TIE 1 transmission interrupt requests 38 and 40 are generated Note A transmission completion interrupt is generated immediately after the transmission interrupts are enabled TIE 1 because the TDRE bit is set to 1 as its initial value TDRE is a read only bit that can be cleared only by...

Page 509: ...e control register SMR0 SMR1 An asynchronous or synchronous baud rate is selected using the machine clock frequency by setting the CS2 to CS0 bits of the mode control register SMR0 SMR1 Baud rates determined using the internal timer The internal clock supplied from 16 bit reload timer 0 is used as it is synchronous or by dividing it by 16 asynchronous for the baud rate Any baud rate can be set by ...

Page 510: ...us clock selection Baud rate Clock selector Down counter Pin P42 SCK0 P62 SCK1 External clock Prescaler UF 16 bit reload timer 0 TMCSR0 TMCSR1 CSL1 CSL0 2 3 SMR0 SMR1 CS2 to CS0 Clock selection bits Dedicated baud rate generator Internal timer φ Machine clock frequency φ φ 21 φ 23 φ 25 When the bits are 110B When the bits are 111B When the bits are 000B to 101B Clock selector φ CDCR0 CDCR1 MD DIV2...

Page 511: ...s baud rates but different values set internally are selected as the transfer clock division ratio for the asynchronous and synchronous baud rates The actual transfer rate can be calculated using the following formulas asynchronous baud rate φ prescaler division ratio asynchronous transfer clock division ratio synchronous baud rate φ prescaler division ratio synchronous transfer clock division rat...

Page 512: ...ontrol register SMR0 SMR1 as listed in Table 17 6 3 Note that the calculation is supposing that φ machine clock 16 MHz div machine clock division ratio 1 Table 17 6 2 Selection of Synchronous Baud Rate Division Ratios CS2 CS1 CS0 CLK synchronization Calculation formula 0 0 0 2 MHz φ div 1 0 0 1 1 MHz φ div 2 0 1 0 500 kHz φ div 4 0 1 1 250 kHz φ div 8 1 0 0 125 kHz φ div 16 1 0 1 62 5 kHz φ div 32...

Page 513: ...timer Note In mode 2 CLK synchronization mode SCK0 SCK1 is up to three clocks later than SCKI A logically attainable transfer rate is 1 3 of the system clock frequency However 1 4 of the system clock frequency is recommended as taken from the actual specifications External clock When CS2 to CS0 are set to 111B and the external clock is selected note the following If the external clock frequency is...

Page 514: ...ratio and reload value for 16 bit reload timer 0 Figure 17 6 2 shows the baud rate selection circuit for the internal timer Figure 17 6 2 Baud Rate Selection Circuit for the Internal Timer 16 bit Reload Timer 0 Baud rate calculation formulas Asynchronous baud rate Synchronous baud rate φ Machine clock frequency X Division ratio for the prescaler of 16 bit reload timer 0 21 23 25 n Reload value for...

Page 515: ...nchronization Clock synchronous X 21 machine cycle divided by 2 X 23 machine cycle divided by 8 X 21 machine cycle divided by 2 X 23 machine cycle divided by 8 38400 2 47 11 19200 5 95 23 9600 11 2 191 47 4800 23 5 383 95 2400 47 11 767 191 1200 95 23 1535 383 600 191 47 9071 767 300 383 95 6143 1535 X Division ratio for the prescaler of 16 bit reload timer 0 Setting not allowed ...

Page 516: ...ins as input ports DDR4 bit2 0 and DDR6 bit2 0 Write 0 to the SCKE bit of the mode control register SMR0 SMR1 to set the pin as an external clock input pin As shown in Figure 17 6 3 a baud rate is selected using the external clock input from the SCK1 pin To change the baud rate the external input clock cycle must be changed because the internal division ratio is fixed Figure 17 6 3 Baud Rate Selec...

Page 517: ...s In the one to one connection method operation mode 0 or 2 must be used in the two CPUs Select operation mode 0 for asynchronous transfer mode and operation mode 2 for synchronous transfer mode Select operation mode 1 for the master slave connection method and use it from the master system Select When parity is disabled for this connection method Synchronization method Asynchronous mode start sto...

Page 518: ...tion operation is disabled during reception data is input to the reception shift register finish frame reception and store the received data in the input data register SIDRI Then stop the reception operation If the transmission operation is disabled during transmission data is output from the transmission shift register wait until there is no data in the output data register SODR0 SODR1 before sto...

Page 519: ... and 1 Transmission operation Transmission data is written to the output data register SODR0 SODR1 when the transmission data empty flag bit SSR0 SSR1 TDRE is 1 This data is transmitted if the transmission operation is enabled SCR0 SCR1 TXE 1 The TDRE flag is again set to 1 when the transmission data is transferred to the transmission shift register and its transmission starts Then the next piece ...

Page 520: ... always checked Error detection In mode 0 parity overrun and framing errors can be detected In mode 1 overrun and framing errors can be detected but parity errors cannot be detected Parity 0 Parity can only be used in operation mode 0 asynchronous normal mode Whether to provide parity can be specified using the PEN bit of the control register SCR0 SCR1 Even or odd parity can also be specified usin...

Page 521: ...ion and reception bits must be supplied When the internal clock dedicated baud rate generator or internal timer is selected the data receiving synchronous clocks is generated automatically if data is transmitted When the external clock is selected confirm that the transmission side UART output data register SODR0 SODR1 contains data SSR0 SSR1 TDRE 0 Then clocks for just 1 byte must be supplied fro...

Page 522: ...REC 0 the error flag is cleared for initialization RXE TXE At least one of the two bits is set to 1 Status register SSR0 SSR1 RIE 1 when using interrupts 0 when using no interrupts TIE 1 when using interrupts 0 when using no interrupts Starting communication Write data to the output data register SODR0 SODR1 to start communication Temporary data must be written to SODR0 SODR1 to start communicatio...

Page 523: ...Figure 17 7 4 Settings for UART Operation Mode 0 Inter CPU connection As shown in Figure 17 7 5 interconnect two CPU s Figure 17 7 5 Connection Example of UART Bidirectional Communication CL AD TXE REC PEN P SBL SCR0 SCR1 SMR0 SMR1 0 0 0 0 1 0 1 0 RIE TIE CS1 CS0 SCKESOE RST MD1 MD0 CS2 RDRFTDRE PE OREFRE SSR0 SSR1 SIDR0 SIDR1 SODR0 SODR1 DDR4 UART0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0 1 Mode 0...

Page 524: ...6 shows an example of a bidirectional communication flowchart Figure 17 7 6 Example of Bidirectional Communication Flowchart NO NO YES YES Transmitting system Receiving system Start Start Set operation mode 0 or 2 Set operation mode same mode as that for the transmitting side Set 1 byte data in UODR and perform communication Data transmission Data transmission Any received data Any received data R...

Page 525: ... Figure 17 7 8 a communication system consists of one master CPU and multiple slave CPUs connected to two communication lines UART can be used only from the master CPU Figure 17 7 8 Connection Example of UART Master slave Communication CL AD TXE REC PEN P SBL SCR0 SCR1 SMR0 SMR1 0 1 0 0 1 0 RIE TIE CS1 CS0 SCKE SOE RST MD1 MD0 CS2 RDRFTDRE PE OREFRE SSR0 SSR1 SIDR0 SIDR1 SODR0 SODR1 DDR4 UART0 Set...

Page 526: ...U checks the address data using a program When the address data indicates the address assigned to a slave CPU the slave CPU communicates with the master CPU ordinary data Figure 17 7 9 shows a flowchart of master slave communication multiprocessor mode Table 17 7 2 Selection of the Master slave Communication Function Operation mode Data Parity Synchronizati on method Stop bit Master CPU Slave CPU ...

Page 527: ... YES End NO YES Master CPU Select transfer mode 1 Set the data for selecting the slave Set 0 in A D Reception is enabled Communication with the slave CPU End communication Communicate with Reception is disabled CPUs in D0 to D7 and set 1 in A D to transfer one byte other slave CPU ...

Page 528: ...munication mode while the system is not operating If the mode is set during transmission or reception the transmission or reception data is not guaranteed Synchronous mode UART clock synchronous mode operation mode 2 uses clock control I O extended serial mode in which start and stop bits are not added to the data Transmission interrupt enabling timing The default initial value of the transmission...

Page 529: ...n interrupt control register DDR6 EQU 000016H Port 6 data direction register CDCR1 EQU 00001BH Communication prescaler register 1 SMR1 EQU 000024H Mode control register 1 SCR1 EQU 000025H Control register 1 SIDR1 EQU 000026H Input data register 1 SODR1 EQU 000026H Output data register 1 SSR1 EQU 000027H Status register 1 REC EQU SCR1 2 Reception error flag clear bit Main program CODE CSEG ABS 0FFH...

Page 530: ... PS to level 7 OR CCR 40H Enables interrupts LOOP MOV A 00H Endless loop MOV A 01H BRA LOOP Interrupt program WARI MOV A SIDR1 Reads receive data CLRB I REC Clears reception interrupt request flag User processing RETI Returns from the interrupt CODE ENDS Vector setting VECT CSEG ABS 0FFH ORG 0FF68H Sets vector for interrupt 37 25H DSL WARI ORG 0FFDCH Sets reset vector DSL START DB 00H Sets single ...

Page 531: ...512 CHAPTER 17 UART ...

Page 532: ... of the DTP External Interrupt Circuit 18 2 Block Diagram of the DTP External Interrupt Circuit 18 3 DTP External Interrupt Circuit Pins 18 4 DTP External Interrupt Circuit Registers 18 5 Operation of the DTP External Interrupt Circuit 18 6 Usage Notes on the DTP External Interrupt Circuit 18 7 Sample Programs for the DTP External Interrupt Circuit ...

Page 533: ...function which performs automatic data transfer using EI2 OS and branches to an interrupt processing routine after the data transfer has been performed a specified number of times Table 18 1 1 provides an overview of the DTP external interrupt circuit Table 18 1 1 Overview of the DTP external Interrupt Circuit External interrupt function DTP function Input pins Eight P10 INT0 DTTI0 to P16 INT6 P63...

Page 534: ... Interrupt control register Vector table address EI2 OS Register name Address Lower Middle Upper INT0 INT1 20 14H ICR04 0000B4H FFFFACH FFFFADH FFFFAEH O INT2 INT3 22 16H ICR05 0000B5H FFFFA4H FFFFA5H FFFFA6H INT4 INT5 25 19H ICR07 0000B7H FFFF98H FFFF99H FFFF9AH INT6 INT7 27 1BH ICR08 0000B8H FFFF90H FFFF91H FFFF92H O Can be used and interrupt request flag is cleared by EI2 OS interrupt clear sig...

Page 535: ... of the DTP external Interrupt Circuit P10 INT0 DTTI0 Pin P11 INT1 Pin P12 INT2 DTTI1 Pin P13 INT3 Pin P14 INT4 Pin P15 INT5 TIN0 Pin LB7 LA7 LB6 LA6 LB5 LA5 LB4 LA4 LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0 P16 INT6 TO0 Pin P63 INT7 Pin Selector Selector Selector Selector Selector Selector Selector Selector ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0 EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0 Interrupt request number 20 14H 22 1...

Page 536: ...use register EIRR that corresponds to the pin Request level setting register ELVR This register selects the effective level or edge for each pin DTP interrupt cause register EIRR This register stores DTP external interrupt causes It contains an external interrupt request flag bit for each pin The bit is set to 1 if a valid signal is input to the corresponding pin DTP interrupt enable register ENIR...

Page 537: ...tor Standby control Setting required to use pins P10 INT0 DTTI0 Port 1 input output external interrupt input resource input output CMOS output CMOS hysteresis input Selectable Provided Set the pin as an input port DDR1 bit8 0 P11 INT1 Set the pin as an input port DDR1 bit9 0 P12 INT2 DTTI1 Set the pin as an input port DDR1 bit10 0 P13 INT3 Set the pin as an input port DDR1 bit11 0 P14 INT4 Set the...

Page 538: ... Port data register PDR PDR read PDR write Output latch DDR read DDR write Direction latch Port data direction register DDR Pin Standby control SPL 1 Resource output Resource output enable RDR Pull up resistor Resource input About 50k Port data register PDR PDR read PDR write Output latch DDR read DDR write Direction latch Port data direction register DDR Pin Standby control SPL 1 Resource output ...

Page 539: ...5 4 3 2 1 0 DTP Interrupt Cause Register DTP Interrupt Enable Register EIRR ENIR Initial value Read write R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 Initial value Read write EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0 15 14 13 12 11 10 9 8 R W 0 Address 000033H R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 LB7 LA7 LB6 LA6 LB5 LA5 LB4 LA4 Address 000032H 7 6 5 4 3 2 1 0 Request Level Setting Register Upper Re...

Page 540: ...ared No effect 0 1 Read Write ER7 ER0 R W Read write 15 bit 14 13 12 11 10 9 8 7 0 R W R W R W R W Table 18 4 1 Function Description of Each Bit of the DTP interrupt Cause Register EIRR Bit name Function bit15 to bit8 ER7 to ER0 External interrupt request flag bits Each of these bits is set to 1 if a signal with the edge or level selected by bits LB7 LA7 to LB0 LA0 of the request level setting reg...

Page 541: ...lue bit 0 1 2 3 4 5 6 7 8 15 Table 18 4 2 Function Description of Each Bit of the DTP interrupt Enable Register ENIR Bit name Function bit7 to bit0 EN7 to EN0 External interrupt request enable bits Each of these bits enables and disables the output of interrupt requests to the CPU If these bits and corresponding bits ER7 to ER0 of the DTP interrupt cause register EIRR are 1 an interrupt request is...

Page 542: ...annel DTP external interrupt pin Interrupt number External interrupt request flag bit External interrupt request enable bit P63 INT7 27 1BH ER7 EN7 P16 INT6 ER6 EN6 P15 INT5 25 19H ER5 EN5 P14 INT4 ER4 EN4 P13 INT3 22 16H ER3 EN3 P12 INT2 DTTI1 ER2 EN2 P11 INT1 20 14H ER1 EN1 P10 INT0 DTTI0 ER0 EN0 Pin name not applicable to MB90465 series ...

Page 543: ...TP external interrupt pin the external interrupt request flag bit is set to 1 regardless of the settings of the DTP interrupt enable register ENIR Table 18 4 5 Correspondence between Request Level Setting Register ELVR and Each Channel DTP external interrupt pin Interrupt number Bit name P63 INT7 27 1BH LB7 LA7 P16 INT6 LB6 LA6 P15 INT5 25 19H LB5 LA5 P14 INT4 LB4 LA4 P13 INT3 22 16H LB3 LA3 P12 I...

Page 544: ...se register EIRR 5 Set the target bit of the DTP interrupt enable register ENIR to enable interrupts The procedure for setting the DTP external interrupt circuit registers must start with disabling the output of external interrupt requests ENIR EN7 to EN0 0 Before the output of external interrupt requests can be enabled ENIR EN7 to EN0 1 the corresponding interrupt request flag bits must be cleare...

Page 545: ...I2 OS the other interrupt requests cannot use it Operation of the DTP external Interrupt Circuit Table 18 5 1 shows the control bits and interrupt causes of the DTP external interrupt circuit When DTP external input requests are set the resource will generate an interrupt request signal to the interrupt controller whenever an interrupt cause indicated in the request level setting register ELVR is ...

Page 546: ...ELVR ICRYY ICRXX CMP CMP DTP handling routine EI2OS is started Transfer data between memory and peripheral Update descriptor Descriptor data counter Interrupt processing routine Set again or stop Return to CPU processing 0 0 1 ICR ISE Start interrupt processing microprogram 0 Accepted by CPU Accepted by interrupt controller Generation of DTP external interrupt request Start external interrupt flag...

Page 547: ...upt level ICR IL2 to IL0 in relation to those of the interrupt requests from other peripheral functions the interrupt priority etc The CPU checks the magnitudes of the interrupt level mask register PS ILM2 to ILM0 and the interrupt level the interrupt enable bit PS CCR 1 etc When the interrupt request is accepted by the CPU the CPU executes an internal interrupt processing routine microprogram and...

Page 548: ...ared to wait for the next request from the pin When the entire transfer using EI2OS is completed control is transferred to the interrupt processing routine The external peripheral must remove only the level of the data transfer request signal DTP external interrupt cause within three cycles of the first transfer Figure 18 5 3 Example of Interfacing to the External Peripheral Input to the INTO pin ...

Page 549: ... is level setting the pulse width requires a longer period than the minimum pulse width stated on the data sheet Also as long as the interrupt input pin retains the active level interrupt requests continue to be generated to the interrupt controller even if the DTP external interrupt cause register is cleared If the register is set for level detection and the level to be detected as an interrupt c...

Page 550: ...rupt processing routine the external interrupt request flag bit must be cleared When the DTP function is used EI2 OS automatically clears the bit For level detection the external interrupt request flag bit is set again as soon as it is cleared if the level assumed as an interrupt cause continues to be input Either disable the output of interrupt requests or remove the interrupt cause if required H...

Page 551: ...rrupt cause register ELVRL EQU 000032H Request level setting register ELVRH EQU 000033H Request level setting register ER0 EQU EIRR 0 INT0 interrupt flag bit EN0 EQU ENIR 0 INT0 interrupt enable bit Main program CODE CSEG START Assumes that stack pointer SP has already been initialized MOV I DDR1 00000000B Sets DDR1 as an input port AND CCR 0BFH Disables interrupts MOV I ICR04 00H Interrupt level ...

Page 552: ...egister ENIR EQU 000030H DTP interrupt enable register EIRR EQU 000031H DTP interrupt cause register ELVRL EQU 000032H Request level setting register ELVRH EQU 000033H Request level setting register ER0 EQU EIRR 0 INT0 interrupt flag bit EN0 EQU ENIR 0 INT0 interrupt enable bit BAPL EQU 000100H Buffer address pointer lower BAPM EQU 000101H Buffer address pointer middle BAPH EQU 000102H Buffer addr...

Page 553: ...0 Clears the cause of INT0 using EIRR SETB I EN0 Enables INT0 using ENIR MOV ILM 07H Sets ILM in PS to level 7 OR CCR 40H Enables interrupts LOOP MOV A 00H Endless loop MOV A 01H BRA LOOP Interrupt program WARI CLRB I ER0 Clears the interrupt request flag Switches the channel and changes the transfer address if required User processing Specifies processing again such as the termination of EI2OS To...

Page 554: ...tions and operation of the delayed interrupt generator module 19 1 Overview of the Delayed Interrupt Generator Module 19 2 Delayed Interrupt Generator Module Register 19 3 Operation of the Delayed Interrupt Generator Module 19 4 Usage Notes on the Delayed Interrupt Generator Module ...

Page 555: ... using this module software can issue and cancel interrupt requests for the F2 MC 16LX CPU Block Diagram of the Delayed Interrupt Generator Module Figure 19 1 1 shows the block diagram of the delayed interrupt generator module Figure 19 1 1 Block Diagram of the Delayed Interrupt Generator Module F 2 MC 16LX bus Delayed interrupt cause issuance cancellation decoder Interrupt cause latch ...

Page 556: ...terrupt Generator Module Register DIRR Bit name Function bit15 to bit9 Reserved bits Both 0 and 1 may be written to the reserved bit area however the set bit and clear bit instructions should be used to access this register to prepare for future expansion bit8 R0 Delayed interrupt request bit This bit is used to controls the generation or clearing of a delayed interrupt request Writing 1 to this r...

Page 557: ...interrupt controller generates an interrupt request to the F2MC 16LX CPU The F2MC 16LX CPU compares the ILM bit of the internal CCR register and the interrupt request When the request level is higher than that of the ILM bit the CPU starts the hardware interrupt processing microprogram immediately after execution of the current instruction ends As a result the interrupt processing routine for this...

Page 558: ... module are given below Usage Notes on the Delayed Interrupt Request Latch This latch is set by writing 1 to the relevant bit of DIRR and cleared by writing 0 to the same bit Note that interrupt processing is restarted at the moment control returns from interrupt processing unless software is created to clear the cause in the interrupt processing routine ...

Page 559: ...540 CHAPTER 19 DELAYED INTERRUPT GENERATOR MODULE ...

Page 560: ...ins 20 4 8 10 bit A D Converter Registers 20 5 8 10 bit A D Converter Interrupts 20 6 Operation of the 8 10 bit A D Converter 20 7 Usage Notes on the 8 10 bit A D Converter 20 8 Sample Program 1 for the 8 10 bit A D Converter Single Conversion Mode Using EI2 OS 20 9 Sample Program 2 for the 8 10 bit A D Converter Continuous Conversion Mode Using EI2 OS 20 10 Sample Program 3 for the 8 10 bit A D C...

Page 561: ... by a program At the end of A D conversion an interrupt request can be generated and EI2 OS can be activated In the interrupt enabled state the conversion data protection function prevents any part of the data from being lost through continuous conversion The conversion can be activated by software 16 bit reload timer 1 rising edge and 16 bit free run timer zero detection edge Table 20 1 1 lists t...

Page 562: ... 20 1 2 8 10 bit A D Converter Interrupts and EI2 OS Interrupt no Interrupt control register Vector table address EI OS Register name Address Lower Upper Bank 11 0BH ICR00 0000B0H FFFFD0H FFFFD1H FFFFD2H O O Can be used and interrupt request flag is cleared by EI2 OS interrupt clear signal ...

Page 563: ... channel It also enables or disables interrupt requests checks the interrupt request status and indicates whether the conversion has halted or is in progress A D data register ADCR0 ADCR1 This register holds the result of A D conversion and selects the resolution for A D conversion 16 bit reload timer 1 ADCS0 ADCR0 ADCR1 AVCC AVR AVSS MPX AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 Input circuit Sample and ho...

Page 564: ...og channel selector It samples and maintains the input voltage obtained immediately after the activation of A D conversion This circuit protects the A D conversion from any variations in the input voltage during approximation D A converter This circuit generates a reference voltage for comparison with the input voltage maintained by the sample and hold circuit Comparator This circuit compares the ...

Page 565: ...nverter Pins Function Pin name Pin function Input output signal type Pull up option Standby control I O port setting for using the pin Channel 0 P50 AN0 Port 5 input output or analog input CMOS output CMOS hysteresis input or analog input Not selectable Not selectable Set port 5 as an input port DDR5 bit8 to bit15 0 Set port 5 as an analog input port ADER bit8 to bit15 1 Channel 1 P51 AN1 Channel ...

Page 566: ... 465 series runs only in single chip mode so only internal ROM and RAM and internal peripheral address space can be accessed To use the pin as an analog input pin set the corresponding bit of the ADER register to 1 The value read from the PDR5 register is 0 ...

Page 567: ...0037H W 0 W 0 W 0 W 0 R X R X S10 ST1 ST0 CT1 CT0 D9 D8 Address 000036H 7 6 5 4 3 2 1 0 A D Data Register Upper A D Data Register Lower ADCR1 ADCR0 Initial value Read write R X R X R X R X R X R X R X R X Initial value Read write D7 D6 D5 D4 D3 D2 D1 D0 15 14 13 12 11 10 9 8 R W 0 Address 000035H R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 W 0 PAUS STS1 STS0 STRT RESV Address 000034H 7 6 5 4 3 2 1 0 A D C...

Page 568: ...ted A D conveision is halted A D conversion is in progress Clears this bit No effect Stops the A D conversion No effect 0 1 Read Write Read Write BUSY 0 1 STRT A D conversion activation bit valid only when activated by software ADC2 EXT 0 Reserved bit RESV Always write 0 to this bit R W R W R W R W R W R W R W W STS1 STS0 A D activation select bit 0 0 1 1 0 1 0 1 Activation by software Activation ...

Page 569: ...egister In continuous conversion mode if a conversion result were written before the previous conversion result was read by the CPU the previous result would be lost When continuous conversion mode is selected the program must be written so that the conversion result is automatically transferred to memory by EI OS each time a conversion is completed This bit also protects against multiple interrup...

Page 570: ...1 ANE1 ANE0 A D conversion end channel select bits AN0 pin AN1 pin AN2 pin AN3 pin AN4 pin AN5 pin AN6 pin AN7 pin ANS2 0 0 0 1 Halt Number of the current conversion channel Number of the last conversion channel Read during conversion Read during a pause in stop conversion mode 0 0 1 1 1 0 0 0 0 1 0 0 1 1 1 1 0 1 1 1 ANS1 ANS0 A D conversion start channel select bits MD1 MD0 A D conversion mode se...

Page 571: ...uring operation is not allowed In the pause state the conversion is reactivated when an activation cause selected by the STS1 and STS0 bits is generated Note In the single conversion modes continuous conversion mode and stop conversion mode no reactivation by a timer external trigger or software is allowed bit5 to bit3 ANS2 to ANS0 A D conversion start channel select bits These bits set the A D co...

Page 572: ...s specify the channel specified by ANS2 to ANS0 just that channel is converted In continuous or stop conversion mode the start channel specified by ANS2 to ANS0 is converted after the channel specified by these bits If the start channel is greater than the end channel the start channel to AN7 and AN0 to the end channel are converted in that order in a single series of conversions Table 20 4 2 A D ...

Page 573: ...50µs 8MHz 66 machine cycles 4 12µs 16MHz 88 machine cycles 5 50µs 16MHz 176 machine cycles 11 0µs 16MHz 20 machine cycles 2 5µs 8MHz 32 machine cycles 2 0µs 16MHz 48 machine cycles 3 0µs 16MHz 128 machine cycles 8 0µs 16MHz 10 bit resolution mode D9 to D0 8 bit resolution mode D7 to D0 S10 AD data bit AD data bits Comparison time setting bits 0 1 0 0 1 1 0 1 0 1 0 0 1 1 0 1 0 1 000037H S10 ST1 ST0...

Page 574: ...ed during the time set in this bit Note Setting these bits to 00B for 8 MHz during 16 MHz operation may disable normal fetching of the analog voltage bit12 bit11 CT1 CT0 Comparison time setting bits These bits select the comparison time for A D conversion After analog input is fetched i e sampling time elapses conversion result data is defined and stored in bit9 to bit0 of this register after the ...

Page 575: ...er Interrupts and EI2 OS EI2 OS Function of the 8 10 bit A D Converter Using the EI2 OS function the 8 10 bit A D converter can transfer the A D conversion result to memory When the transfer is performed a conversion data protection function halts the A D conversion until the A D conversion data is transferred to memory and clears the INT bit The function prevents any part of the data from being l...

Page 576: ...nversion Mode Reference The following are sample conversion sequences in single conversion mode ANS 000B ANE 011B AN0 AN1 AN2 AN3 End ANS 110B ANE 010B AN6 AN7 AN0 AN1 AN2 End ANS 011B ANE 011B AN3 End Operation in Continuous Conversion Mode In continuous conversion mode the analog inputs from the channel specified by the ANS bits to the channel specified by the ANE bits are sequentially converted...

Page 577: ...ied by the ANS bits If the start and end channels are the same ANS ANE the conversion of the channel specified by the ANS bits is repeated To reactivate conversion during a pause generate the activation cause specified by the STS1 and STS0 bits Figure 20 6 3 shows the settings required for operation in stop conversion mode Figure 20 6 3 Settings for Stop Conversion Mode ADCS BUSY INT INTE PAUS STS...

Page 578: ...erence The following are sample conversion sequences in stop conversion mode ANS 000B ANE 011B AN0 Pause AN1 Pause AN2 Pause AN0 Repeat ANS 110B ANE 001B AN6 Pause AN7 Pause AN0 Pause AN1 AN6 Repeat ANS 011B ANE 011B AN3 Pause AN3 Pause Repeat ...

Page 579: ...ed When EI2 OS is used the conversion data protection function prevents any part of the data from being lost even in continuous conversion Multiple data items can be safely transferred to memory Starting A D conversion Sample and hold Conversion End of conversion Issuing interrupt Starting EI2OS Transferring data Clearing interrupt Interrupt processing The number of timers is determined according ...

Page 580: ...ed When conversion data is stored in the A D data register ADCR0 ADCR1 the INT bit of the A D control status register1 ADCS1 is set to 1 While the INT bit is 1 A D conversion is halted Halt status is released when the INT bit is cleared after data in the A D data register ADCR0 ADCR1 has been transferred to memory by the interrupt routine Data protection function when EI2 OS is used In continuous ...

Page 581: ...ata is transferred Reactivation attempted during a pause will cause the old data to be destroyed Reactivation attempted during a pause will destroy the standby data Set EI2OS Start continuous A D conversion End first conversion Store data in the data register End second conversion Has EI2OS ended Store data in the data register Third conversion Terminate all conversions Store data in the data regi...

Page 582: ...leakage current flows through the gate Note on using an internal timer To start the A D converter with an internal timer set the STS1 and STS0 bits of A D control status register 1 ADCS1 accordingly Set the input value of the internal timer at the inactive level L for the internal timer Otherwise operation may start concurrently with writing to the ADCS register Sequence of turning on the A D conv...

Page 583: ...8 1 Flowchart of Program using EI2OS Single Conversion Mode Coding example BAPL EQU 000100H Lower buffer address pointer BAPM EQU 000101H Intermediate buffer address pointer BAPH EQU 000102H Upper buffer address pointer ISCS EQU 000103H EI2 OS status register IOAL EQU 000104H Lower I O address register IOAH EQU 000105H Upper I O address register DCTL EQU 000106H Lower data counter DCTH EQU 000107H...

Page 584: ...ress pointer MOV DCTL 03H Sets the EI2 OS transfer count to three which is the same value as the conversion count MOV DDR5 11110001B Sets P51 to P53 as input MOV ADER 00001110B Sets P51 AN1 to P53 AN3 as analog inputs MOV DCTH 00H MOV ADCS0 0BH Single activation Converts AN1 to AN3 MOV ADCS1 0A2H Software activation Begins A D conversion Enables interrupts MOV ILM 07H Sets ILM in PS to level 7 OR ...

Page 585: ...ersion Mode Coding example BAPL EQU 000100H Lower buffer address pointer BAPM EQU 000101H Middle buffer address pointer BAPH EQU 000102H Upper buffer address pointer ISCS EQU 000103H EI2 OS status register IOAL EQU 000104H Lower I O address register IOAH EQU 000105H Upper I O address register DCTL EQU 000106H Lower data counter DCTH EQU 000107H Upper data counter DDR5 EQU 000015H Port 5 direction ...

Page 586: ...s analog input MOV DCTH 00H MOV ADCS0 9DH Continuous conversion mode Converts AN3 to AN5 CH MOV ADCS1 0A8H Activates the 16 bit timer starts A D conversion and enables interrupts MOV WTMRD1 0320H Sets the timer value to 800 320H 100µs MOV TMCSRH1 00H Sets the clock source to 125 ns and disables external trigger MOV TMCSRL1 12H Disables timer output disables interrupts and enables reload MOV TMCSRL...

Page 587: ...Stop Conversion Mode Coding example BAPL EQU 000100H Lower buffer address pointer BAPM EQU 000101H Middle buffer address pointer BAPH EQU 000102H Upper buffer address pointer ISCS EQU 000103H EI2 OS status register IOAL EQU 000104H Lower I O address register IOAH EQU 000105H Upper I O address register DCTL EQU 000106H Lower data counter DCTH EQU 000107H Upper data counter DDR5 EQU 000015H Port 5 d...

Page 588: ...s input MOV ADER 00001000B Sets P53 AN3 as analog input MOV ADCS0 0DBH Stop conversion mode Converts AN3 CH MOV ADCS1 0A8H Activates the 16 bit timer starts A D conversion and enables interrupts MOV WTMRD1 0320H Sets the timer value to 800 320H 100 µs MOV TMCSRH1 00H Sets the clock source to 125 ns and disables external trigger MOV TMCSRL1 12H Disables timer output disables interrupts and enables ...

Page 589: ...570 CHAPTER 20 8 10 BIT A D CONVERTER ...

Page 590: ...tions and operation of the ROM correction function 21 1 Overview of the ROM Correction Function 21 2 Block Diagram of ROM Correction Function 21 3 ROM Correction Function Registers 21 4 Operation of the ROM Correction Function 21 5 Example of Using ROM Correction Function ...

Page 591: ...upt routine Program Address Detection Registers 2 There are two program address detection registers PADR0 PADR1 each is provided with an interrupt enable bit and interrupt flag ROM Correction Interrupts When the interrupt enable bit is 1 the value set in the program address detection register is compared with the address If the value matches the address 1 is set in the interrupt flag bit and the i...

Page 592: ... The block diagram of ROM correction function is shown as below Block Diagram of ROM Correction Function Figure 21 2 1 Block Diagram of ROM Correction Function Address latch Address detection register 0 1 F2 MC 16LX CPU INT9 command Comparator F 2 MC 16LX bus AD0E AD1E AD0D AD1D PACSR ...

Page 593: ...on Address 1FF2H 1FF1H 1FF0H Address 1FF5H 1FF4H 1FF3H Upper byte Middle byte Lower byte PADR1 Program Address Detection Register 0 1 AD1E AD0E 7 6 5 4 3 2 1 0 Address 00009EH PACSR 0 0 0 0 0 0 0 0 Initial value R W R W R W R W Read write AD1D AD0D Program Address Detection Control Status Register XXXXXXXXB Initial value R W R W R W Read write XXXXXXXXB XXXXXXXXB PADR0 PADRL0 PADRM0 PADRH0 PADRL1 ...

Page 594: ...gister is 1 the corresponding interrupt bit is set to 1 to request the CPU to generate an INT9 instruction If the corresponding interrupt enable bit is 0 no operation is performed Table 21 3 1 lists the correspondence between the program address detection register and PACSR Address 1FF2H 1FF1H 1FF0H Address 1FF5H 1FF4H 1FF3H Upper byte Middle byte Lower byte PADR1 Program Address Detection Registe...

Page 595: ...1 0 Initial value 00009EH AD1E AD1D AD0E AD0D 0000B R W R W R W R W AD0D Address detection flag 0 bit Read Write 0 No address compare match Clear this bit 1 Address compare match No effect AD0E Address detection register 0 enable bit 0 Disable interrupt request 1 Enable interrupt request AD1D Address detection flag 1 bit Read Write 0 No address compare match Clear this bit 1 Address compare match ...

Page 596: ...h detection bit This bit is set to 1 to indicate that the value set in the PADR1 register matches the address It is cleared to 0 by writing 0 to it It is left unchanged by writing 1 to it bit1 AD0E Address detection register 0 enable bit ADR0 operation enable bit When this bit is 1 the value set in the PADR0 register is compared to the address If the two values are equal an INT9 instruction is gen...

Page 597: ...address detection registers of which each is provided with an interrupt enable bit and interrupt flag When the address is equal to the value set in the address detection register and the interrupt enable bit is 1 assume the following the interrupt flag is set to 1 and the instruction code to be read by the CPU is replaced forcibly with the INT9 instruction code The interrupt flag is cleared to 0 b...

Page 598: ...ing 0000H Number of bytes of patch program No 0 0 for no program error 0001H Bit7 to bit0 of program address No 0 0002H Bit15 to bit8 of program address No 0 0003H Bit24 to bit26 of program address No 0 0004H Number of bytes of patch program No 1 0 for no program error 0005H Bit7 to bit0 of program address No 1 0006H Bit15 to bit8 of program address No 1 0007H Bit24 to bit16 of program address No ...

Page 599: ...gram to run The first address of the program written to RAM is saved in RAM as specified for each address detection register INT9 Interrupt During execution of an interrupt routine control checks the interrupt flag for an address in which an interrupt was enabled and branches to the corresponding program The information stacked by the interrupt is deleted The interrupt flag is also cleared Figure ...

Page 600: ...JMP 000400H Patch program execution 000400H to 000480H End of patch program JMP FF0050H INT9 INT9 Normal program execution PC PADR0 NO YES Patch program Size of patch Upper program address 00 Middle program address 00 Lower program address 00 E2 PROM FFFFH 0090H 0010H 0003H 0002H 0001H 0000H program in byte 80 I O area RAM Register area RAM area Stack area FFFFFFH FF0050H FF0000H FE0000H 001100H 0...

Page 601: ...582 CHAPTER 21 ROM CORRECTION FUNCTION ...

Page 602: ...LECTION MODULE This chapter explains the function and operation of the MB90460 465 series ROM mirroring function selection module 22 1 Overview of the ROM Mirroring Function Selection Module 22 2 ROM Mirroring Function Selection Register ROMM ...

Page 603: ...rom bank 00 by setting the register ROM Mirroring Function Selection Module Register ROM Mirroring Function Selection Module Block Diagram Figure 22 1 1 ROM Mirroring Function Selection Module Block Diagram 15 14 13 12 11 10 9 8 Address 00006FH ROMM 1 Initial value W Read write ROM Mirror Function Selection Register MI bit ROM mirroring register ROM 00 bank FF bank Address area F 2 MC 16LX bus ...

Page 604: ... R W R W R W R W R W W R W MI 0 1 ROM mirroring function selection bit Disable ROM mirroring function Enable ROM mirroring function bit8 Reserved 0 Reserved bit Always write 0 to these bits bit15 to bit9 X W R W Readable and writable Write only Indeterminate Initial value MI Table 22 2 1 ROM Mirroring Function Selection Register Bit name Function bit15 to bit9 Reserved bits The read value is undef...

Page 605: ...A MB90F463A MB90V460 Address 1 FF0000H FF0000H FF0000H FF0000H FE0000H FF0000H Address 2 000900H 000900H 000900H 000900H 000900H 002100H ROM area ROM area RAM area I O area I O area RAM area ROM area FFFFFFH Address 1 010000H 004000H 002000H Address 2 000100H 0000C0H 000000H Address Internal area When MI 1 When MI 0 ...

Page 606: ... 23 1 Overview of the 512K 1024K Bit Flash Memory 23 2 512K 1024K Bit Flash Memory Sector Configuration 23 3 Flash Memory Control Status Register FMCS 23 4 Method of Starting the Automatic Algorithm in Flash Memory 23 5 Verifying Automatic Algorithm Execution Status 23 6 Detailed Explanation on the Flash Memory Write Delete 23 7 Flash Security Feature 23 8 Programming Example of 512K Bit Flash Mem...

Page 607: ...x 16 bits 64K 16K 8K 8K 32K sector configuration Automatic program algorithm same as the Embedded Algorithm TM MBM29F400TA Installation of the deletion temporary stop delete restart function Write delete completion detected by the data polling or toggle bit Write delete completion detected by the CPU interrupt Compatibility with the JEDEC standard type command Each sector deletion can be executed ...

Page 608: ... the FE and FF bank register Figure 23 2 2 1024K Bit Flash Memory Sector Configuration Writer address The writer address is equivalent to the CPU address when writing the data to the flash memory using the parallel writer If the write delete operation is executed using the general purpose writer the write delete operation is executed using this address SA3 16 Kbytes SA2 8 Kbytes SA1 8 Kbytes SA0 3...

Page 609: ...fter the write delete operation is terminated and this bit is set to 1 the flash memory can be written or deleted This bit is cleared to 0 by writing 0 and the writing of 1 is ignored At the termination time of the automatic algorithm in the flash memory see 23 4 Method of Starting the Automatic Algorithm in Flash Memory this bit is set to 1 While using the read modify write RMW instruction 1 can ...

Page 610: ... the current consumption in the flash memory when accessing the flash memory However the access time from the CPU to the flash memory greatly dependent upon the setting Therefore the set values should be selected depending on the CPU operating frequency 01 Low power consumption mode Internal operating frequency operating at 4 MHz or less 10 Low power consumption mode Internal operating frequency o...

Page 611: ...can be specified SA Sector address For details see 23 2 512K 1024K Bit Flash Memory Sector Configuration RD Read data PD Write data Only the word data can be specified Table 23 4 1 Command Sequence Table Command sequence Bus write cycle 1st bus write cycle 2nd bus write cycle 3rd bus write cycle 4th bus write cycle 5th bus write cycle 6th bus write cycle Address Data Address Data Address Data Ad d...

Page 612: ...ading the address of the target sector in the flash memory after setting the command sequence see 23 4 Method of Starting the Automatic Algorithm in Flash Memory Table 23 5 1 indicates the hardware sequence flag bit allocation It can be determined whether automatic write chip sector deletion is being performed depending on the end of write processing by checking the hardware sequence flag or the R...

Page 613: ...n operation Deletion completion 0 1 Toggle Stop 0 1 1 Sector deletion wait Deletion start 0 Toggle 0 0 1 Deletion processing Sector deletion temporary stop sector being deleted 0 1 Toggle 1 0 1 0 Sector deletion temporary stop Deletion restart sector being deleted 1 0 1 Toggle 0 0 1 While the sector deletion is being temporarily stopped sector not being deleted DATA 7 DATA 6 DAATA 5 DATA 3 Abnorma...

Page 614: ...ution the flash memory outputs 0 from the sector being deleted by the sector deletion or irrespective of the specified address during the chip deletion Similarly the flash memory outputs 1 at the end of chip sector deletion algorithm When the Sector Deletion Temporary Stop is Executed When the access read is executed while executing the sector deletion temporary stop the flash memory outputs 1 if ...

Page 615: ... Start DQ7 DQ7 DATA 7 0 1 0 1 0 DATA 7 Sector deletion temporary stop Restart Sector being deleted During the sector deletion temporary stop Sector not Sector deletion Deletion temporary stop Sector being deleted 0 1 Operating status Write operation Chip sector deletion operation DQ7 DQ7 0 Status transition during abnormal operation Status transition during normal operation being deleted ...

Page 616: ...uts 1 if the specified address belongs to the sector being deleted The flash memory outputs the data of bit6 DATA 6 in the specified read address unless the specified address belongs to the sector being deleted Reference When executing the write operation the toggle bit executes the toggle operation for about 2 ms then terminates it without rewriting the data if the sector to be written is write p...

Page 617: ...the data polling function or toggle bit function For example a fail occurs if an attempt is made to write 1 to the flash memory with 0 written In this case the flash memory is locked and the automatic algorithm is not terminated Therefore no valid data is set in data polling flag DQ7 The toggle bit flag DQ6 does not stop the toggle operation so the execution time exceeds the time limit Then the ti...

Page 618: ...sh memory accepts the additional sector deletion code to be written To verify this event it is recommended that this flag status be checked before writing the succeeding sector deletion code If this flag is 1 when the second time the status is checked the additional sector deletion code may not be accepted When the Sector Deletion Operation is Executed When the read access is executed while execut...

Page 619: ...stop or deletion start operation can be performed by the automatic algorithm which can be started by setting the command sequence see 23 4 Method of Starting the Automatic Algorithm in Flash Memory to each bus write cycle The write cycles to the respective buses must be executed continuously The ending time of the automatic algorithm can be notified by the data polling function and so on After the...

Page 620: ... executed once and the other is that the bus operations are executed three times However these command sequences have no essential difference The read reset status is the initial status of the flash memory When the power supply is turned on or when the command is normally terminated the flash memory is always set to the read reset status The read reset status means the status of the flash memory t...

Page 621: ...to data 0 the data polling algorithm DQ7 or toggle operation DQ6 is not terminated and the flash memory element is determined to be bad Then the time limit exceeded flag DQ5 error may be determined by the excess of the write defined time or data 1 may be apparently written but is not actually done However if data is read from the flash memory in the read reset status data remains 0 Only the deleti...

Page 622: ...MCS WE bit5 Write command sequence 1 FxAAAA XXAA 2 Fx5554 XX55 3 FxAAAA XXA0 4 Write address Write data Internal address read Data polling DQ7 Next address Data Data Data Data 0 1 Time limit DQ5 Internal address read Data polling DQ7 Write error Last address Flash memo ry write disabled Write completion Verification using the hardware sequence flag FMCS WE bit5 ...

Page 623: ...the command sequence table see 23 4 Method of Starting the Automatic Algorithm in Flash Memory to the target sector in the flash memory The chip deletion command is executed by executing the bus operation six times When the 6th cycle write operation has been completed the chip deletion operation is started The user need not write the data to the flash memory before chip deletion operation During t...

Page 624: ...sector deletion wait period of 50 µs is terminated Thus the next deletion sector address and deletion code i e in the 6th cycle of the command sequence must be input each within 50 µs to delete two or more sectors simultaneously which may not be accepted later than 50 µs It can be checked whether the succeeding sector deletion code write operation is valid using the sector deletion timer flag DQ3 ...

Page 625: ...5 FF5554 Input the code to the sector to be deleted 30H Is there another sector to be deleted Internal adress read 1 Internal adress read 2 Toggle DQ6 Data 1 Data 2 Time limit DQ5 Next sector Internal adress read Internal adress read Toggle bit DQ6 Data 1 Data 2 Last sector FMCS WE bit5 Flash memory deletion disabled Deletion completion Verification using the hardware sequence flag Delete error Se...

Page 626: ...eration cannot be done This command is valid only during the sector deletion operation including the deletion waiting time but it is ignored during the chip deletion operation or the write operation This command is executed by writing the deletion temporary stop code B0H In this case the address must indicate an address within the flash memory During the deletion temporary stop operation the reiss...

Page 627: ...n restart command listed in the command sequence table see 23 4 Method of Starting the Automatic Algorithm in Flash Memory to the target sector in the flash memory The sector deletion restart command is used to restart the sector deletion operation when the flash memory is in the sector deletion temporary stop status caused by the sector deletion temporary stop command This command is executed by ...

Page 628: ...table for applications requiring security of self containing program and data stored in the flash memory If the target application requires any part of the program to locate outside the microcontroller the Flash Security Controller can not offer the intended features For this reason the External Vector Fetch mode should not be used when the protection code is set Programming of the flash microcont...

Page 629: ...d output the value to PDR2 5 Erase the sector SA0 to which the value was written 6 Output a confirmation that the data was erased Requirements Number of bytes transferred to RAM 100 H 256 B Determination that writing or erasing has ended Determined via DQ5 timing limit exceeded flag Determined via DQ6 toggle bit flag Determined via RDY FMCS Error handling Output Hi to P00 to P07 Issue a reset comm...

Page 630: ... 0BC00H Source address location of program MOVW RW0 100H Number of bytes of data transferred to RAM MOVS ADB PCB Transfer 100H from FFBC00H to 000700H CALLP 000700H Jump to the address where the transferred program exists Data output OUT MOV A 0FEH MOV ADB A MOVW RW2 0000H MOVW A RW2 00 MOV PDR2 A END JMP CODE ENDS Flash program write erase program SA2 RAMPRG CSEG ABS 0FFH ORG 0BC00H Initializatio...

Page 631: ...00 AH MOVW A RW2 00 AL XORW A XOR of AH and AL 1 when the values are different AND A 40H Checks whether the DQ6 toggle bit is different BNZ ERROR If it is different branches to ERROR Write end check FMCS RDY NTOW MOVW A FMCS AND A 10H FMCS RDY bit 4 bit is extracted BZ WRITE Verifies that writing has ended MOV FMCS 00H Write mode is released Write data output MOVW RW2 0000H Write data output MOVW ...

Page 632: ... toggled XOR is 1 indicating that writing is in progress AND A 40H Checks whether the DQ6 toggle bit is Hi BNZ ERROR If the bit is Hi branches to ERROR Erase end check FMCS RDY NTOE MOVW A FMCS AND A 10H FMCS RDY bit 4 bit is extracted BZ ELS Verifies that erasing of the sector has ended MOV FMCS 00H Flash memory erase mode is released RETP Returns to the main program Error ERROR MOV ADB COMADR1 0...

Page 633: ...614 CHAPTER 23 512K 1024K BIT FLASH MEMORY ...

Page 634: ...ation for Serial On board Writing Fujitsu Standard 24 2 Example of Connection for Serial Writing When Power Supplied by User 24 3 Example of Connection for Serial Writing When Power Supplied from Writer 24 4 Example of Minimum Connection with Flash Microcontroller Programmer When Power Supplied by User 24 5 Example of Minimum Connection with Flash Microcontroller Programmer When Power Supplied fro...

Page 635: ...l On board Writing Pin Function Description MD2 MD1 MD0 Mode pin Used to enable write mode for the flash microcomputer programmer X0 X1 Oscillator pin In write mode since the operation clock is one times the CPU clock the oscillation clock frequency is the internal operation clock The resonator used for serial rewriting is therefore 1 MHz to 16 MHz P00 P01 Write program start pin RSTX Reset pin SI...

Page 636: ...er programmer when power supplied by user Example of minimum connection to flash microcontroller programmer when power supplied from writer For more information contact the Sales Department Equipment Business Division Yokogawa Digital Computer Co Ltd Telephone 81 42 333 6224 10kΩ MB90F462 F462A F463A write control pin AF200 write control pin AF200 TICS pin User Table 24 1 2 System Configuration of...

Page 637: ...n for Serial Writing when Power Supplied by User Figure 24 2 1 Example of Connection for Serial Writing in MB90F462 F462A F463A Internal Vector Mode when Power Supplied by User P00 MD0 MD1 Vss Vcc GND SCK0 SOT0 SIN0 TRXD TTXD TCK TMODE TAUX3 TICS MD2 TAUX 19 12 23 10 13 27 6 7 8 14 15 21 22 1 28 DX10 28S TRES 5 P01 2 TVcc C X0 X1 1MHz to 16MHz AF200 flash microcontroller programmer User system Con...

Page 638: ... SCK0 the control circuit shown below is necessary just as it is for P00 During serial writing the user circuit can be disconnected by the flash microcontroller programmer TICS signal Before connecting the AF200 turn off the power supplied by the user 10k MB90F462 F462A F463A write control pin AF200 write control pin AF200 TICS pin User ...

Page 639: ... for Serial Writing when Power Supplied from Writer Figure 24 3 1 Example of Connection for Serial Writing in MB90F462 F462A F463A Internal Vector Mode when Power Supplied from Writer P00 MD0 MD1 Vss Vcc GND SCK0 SOT0 SIN0 TRXD TTXD TCK TMODE TAUX3 TICS MD2 TAUX 19 12 23 10 13 27 6 7 8 14 15 21 22 1 28 DX10 28S TRES 5 P01 2 TVcc C X0 X1 1MHz to 16MHz AF200 flash microcontroller programmer User sys...

Page 640: ...s necessary just as it is for P00 During serial writing the user circuit can be disconnected by the flash microcontroller TICS signal Before connecting the AF200 turn off the power supplied by the user When supplying write power from the AF200 do not create a short with the power supplied by the user 10k MB90F462 F462A F463A write control pin AF200 write control pin AF200 TICS pin User ...

Page 641: ... writing to flash memory MD2 MD1 MD0 P00 and flash microcontroller programmer connection is unnecessary Figure 24 4 1 Example of Minimum Connection with Flash Microcomputer Programmer when Power Supplied by User MD1 Vss GND MD2 MB90F462 F462A 463A 7 8 14 15 21 22 1 28 DX10 28S SIN0 TTXD 13 SOT0 TRXD 27 SCK0 TCK 6 Vcc 2 TVcc MD0 TRES RSTX 5 P00 P01 C X0 X1 1MHz to 16MHz Pins 3 4 9 10 11 12 16 17 18...

Page 642: ...SOT0 and SCK0 pins the control circuit shown below is necessary During serial writing the user circuit can be disconnected by the flash microcontroller programmer TICS signal Before connecting the AF200 turn off the power supplied by the user 10k MB90F462 F462A F463A write control pin AF200 write control pin AF200 TICS pin User ...

Page 643: ... MD2 MD1 MD0 P00 and flash microcontroller programmer connection is unnecessary Figure 24 5 1 Example of Minimum Connection with Flash Microcontroller Programmer when Power Supplied from Writer MD1 Vss GND MD2 MB90F462 F462A F463A 7 8 14 15 21 22 1 28 DX10 28S SIN0 TTXD 13 SOT0 TRXD 27 SCK0 TCK 6 MD0 TRES RSTX 5 P00 P01 Vcc TVPP1 3 2 TVcc Vcc 16 C X0 X1 1MHz to 16MHz Serial write1 AF200 flash micr...

Page 644: ...is necessary During serial writing the user circuit can be disconnected by the flash microcontroller programmer TICS signal Before connecting the AF200 turn off the power supplied by the user When write power is supplied from the AF200 do not create a short with the power supplied by user 10k MB90F462 F462A F463A write control pin AF200 write control pin AF200 TICS pin User ...

Page 645: ...626 CHAPTER 24 EXAMPLE OF F2 MC 16LX MB90F462 F462A F463A CONNECTION FOR SERIAL WRITING ...

Page 646: ...627 APPENDIX The appendixes contain an I O map and F2 MC 16LX instructions description APPENDIX A I O MAP APPENDIX B Instructions ...

Page 647: ... Prohibited area 000010H DDR0 Port 0 direction register R W R W Port 0 00000000B 000011H DDR1 Port 1 direction register R W R W Port 1 00000000B 000012H DDR2 Port 2 direction register R W R W Port 2 00000000B 000013H DDR3 Port 3 direction register R W R W Port 3 00000000B 000014H DDR4 Port 4 direction register R W R W Port 4 0000000B 000015H DDR5 Port 5 direction register R W R W Port 5 00000000B ...

Page 648: ...DCR1 R W R W 00000 XXB 000038H PDCR0 PPG0 down counter register R 16 bit PPG timer CH 0 11111111B 000039H 11111111B 00003AH PCSR0 PPG0 period setting register W XXXXXXXXB 00003BH XXXXXXXXB 00003CH PDUT0 PPG0 duty setting register W XXXXXXXXB 00003DH XXXXXXXXB 00003EH PCNTL0 PPG0 control status register lower byte R W R W 000000B 00003FH PCNTH0 PPG0 control status register upper byte R W R W 000000...

Page 649: ...0 R 16 bit input capture CH 0 to CH 3 XXXXXXXXB 000061H Input capture data register CH 0 R XXXXXXXXB 000062H IPCP1 Input capture data register CH 1 R XXXXXXXXB 000063H Input capture data register CH 1 R XXXXXXXXB 000064H IPCP2 Input capture data register CH 2 R XXXXXXXXB 000065H Input capture data register CH 2 R XXXXXXXXB 000066H IPCP3 Input capture data register CH 3 R XXXXXXXXB 000067H Input ca...

Page 650: ...XXXXXB 000085H XXXXXXXXB 000086H TMCSRL1 Timer control status register CH 1 lower byte R W R W 16 bit reload timer CH 1 00000000B 000087H TMCSRH1 Timer control status register CH 1 upper byte R W R W 0000B 000088H TMR1 TMRD1 16 bit timer register 16 bit reload register CH 1 R W XXXXXXXXB 000089H XXXXXXXXB 00008AH OPCLR Output control lower register R W R W Waveform sequencer 00000000B 00008BH OPCU...

Page 651: ...rrupt control register 11 R W R W 00000111B 0000BCH ICR12 Interrupt control register 12 R W R W 00000111B 0000BDH ICR13 Interrupt control register 13 R W R W 00000111B 0000BEH ICR14 Interrupt control register 14 R W R W 00000111B 0000BFH ICR15 Interrupt control register 15 R W R W 00000111B 0000C0H to FFH External area 001FF0H PADRL0 Program address detection register 0 lower byte R W R W Address ...

Page 652: ...fer register 6 R W 00000000B 003FEEH OPEBR7 Output data buffer register 7 R W 00000000B 003FEFH Output data buffer register 7 R W 00000000B 003FF0H OPEBR8 Output data buffer register 8 R W 00000000B 003FF1H Output data buffer register 8 R W 00000000B 003FF2H OPEBR9 Output data buffer register 9 R W 00000000B 003FF3H Output data buffer register 9 R W 00000000B 003FF4H OPEBRA Output data buffer regi...

Page 653: ...tion of initial values 0 The bit is initialized to 0 1 The bit is initialized to 1 X The initial value of the bit is undefined The bit is not used Its initial value is undefined Instruction using IO addressing e g MOV A io is not supported for registers area 003FE0H to 003FFFH These registers are not present in MB90465 series ...

Page 654: ...nstructions used by the F2MC 16LX B 1 Instruction Types B 2 Addressing B 3 Direct Addressing B 4 Indirect Addressing B 5 Execution Cycle Count B 6 Effective address field B 7 How to Read the Instruction List B 8 F2 MC 16LX Instruction List B 9 Instruction Map Code CM44 10120 3EB ...

Page 655: ...d 12 increment decrement instructions byte word or long word 11 comparison instructions byte word or long word 11 unsigned multiplication division instructions word or long word 11 signed multiplication division instructions word or long word 39 logic instructions byte or word 6 logic instructions long word 6 sign inversion instructions byte or word 1 normalization instruction long word 18 shift i...

Page 656: ...t branch address addr24 I O direct io Abbreviated direct address dir Direct address addr16 I O direct bit address io bp Abbreviated direct bit address dir bp Direct bit address addr16 bp Vector address vct Register indirect RWj j 0 to 3 Register indirect with post increment RWj j 0 to 3 Register indirect with displacement RWi disp8 i 0 to 7 RWj disp16 j 0 to 3 Long register indirect with displacem...

Page 657: ...er indirect DTB 09 RW1 DTB 0A RW2 ADB 0B RW3 SPB 0C RW0 Register indirect with post increment DTB 0D RW1 DTB 0E RW2 ADB 0F RW3 SPB 10 RW0 disp8 Register indirect with 8 bit displacement DTB 11 RW1 disp8 DTB 12 RW2 disp8 ADB 13 RW3 disp8 SPB 14 RW4 disp8 Register indirect with 8 bit displacement DTB 15 RW5 disp8 DTB 16 RW6 disp8 ADB 17 RW7 disp8 SPB 18 RW0 disp16 Register indirect with 16 bit displ...

Page 658: ... instruction stores the operand value in A Before execution A 2 2 3 3 4 4 5 5 After execution A 4 4 5 5 1 2 1 2 Some instructions transfer AL to AH Table B 3 1 Direct Addressing Registers General purpose register Byte R0 R1 R2 R3 R4 R5 R6 R7 Word RW0 RW1 RW2 RW3 RW4 RW5 RW6 RW7 Long word RL0 RL1 RL2 RL3 Special purpose register Accumulator A AL Pointer SP Bank PCB DTB USB SSB ADB Page DPR Control ...

Page 659: ...t16 of the address are specified by the program counter bank register PCB Figure B 3 3 Example of Direct Branch Addressing addr16 MOV R0 A This instruction transfers the eight low order bits of A to the general purpose register R0 Before execution A 0 7 1 6 2 5 3 4 Memory space R0 After execution A 0 7 1 6 2 5 6 4 Memory space R0 3 4 JMP 3B20H This instruction causes an unconditional branch by dir...

Page 660: ...00FFH is accessed regardless of the data bank register DTB and direct page register DPR A bank select prefix for bank addressing is invalid if specified before an instruction using I O direct addressing Figure B 3 5 Example of I O Direct Addressing io JMPP 333B20H This instruction causes an unconditional branch by direct branch 24 bit addressing Before execution PC 3 C 2 0 PCB 4 F Memory space 333...

Page 661: ...pecified by the data bank register DTB A prefix instruction for access space addressing is invalid for this mode of addressing Figure B 3 7 Example of Direct Addressing addr16 MOV S 20H A This instruction writes the contents of the eight low order bits of A in abbreviated direct addressing mode Before execution A 4 4 5 5 1 2 1 2 Memory space DPR 6 6 DTB 7 7 776620H After execution A 4 4 5 5 1 2 1 ...

Page 662: ...it LSB Figure B 3 9 Example of Abbreviated Direct Bit Addressing dir bp Direct bit addressing addr16 bp Specify arbitrary bits in 64 kilobytes explicitly Address bits 16 to 23 are specified by the data bank register DTB Bit positions are indicated by bp where the larger number indicates the most significant bit MSB and the lower number indicates the least significant bit LSB Figure B 3 10 Example ...

Page 663: ...o the address indicated by the interrupt vector specified in an operand Before execution PC 0 0 0 0 Memory space PCB F F FFC000H E F CALLV 15 After execution PC D 0 0 0 FFFFE0H 0 0 PCB F F FFFFE1H D 0 Table B 3 2 CALLV Vector List Instruction Vector address L Vector address H CALLV 0 XXFFFEH XXFFFFH CALLV 1 XXFFFCH XXFFFDH CALLV 2 XXFFFAH XXFFFBH CALLV 3 XXFFF8H XXFFF9H CALLV 4 XXFFF6H XXFFF7H CAL...

Page 664: ...ister RWj as an address After operand operation RWj is incremented by the operand size 1 for a byte 2 for a word or 4 for a long word Address bits 16 to 23 are indicated by the data bank register DTB when RW0 or RW1 is used system stack bank register SSB or user stack bank register USB when RW3 is used or additional data bank register ADB when RW2 is used If the post increment results in the addre...

Page 665: ...ack bank register USB when RW3 or RW7 is used or additional data bank register ADB when RW2 or RW6 is used Figure B 4 3 Example of Register Indirect Addressing with Offset RWi disp8 i 0 to 7 RWj disp16 j 0 to 3 MOVW A RW1 This instruction reads data by register indirect addressing with post increment and stores it in A Before execution A 0 7 1 6 2 5 3 4 Memory space RW1 D 3 0 F DTB 7 8 78D30FH E E...

Page 666: ... of each of the following instructions is not deemed to be next instruction address disp16 DBNZ eam rel DWBNZ eam rel CBNE eam imm8 rel CWBNE eam imm16 rel MOV eam imm8 MOVW eam imm16 Figure B 4 5 Example of Program Counter Indirect Addressing with Offset PC disp16 MOVW A RL2 25H This instruction reads data by long register indirect addressing with an offset and stores it in A Before execution A 0...

Page 667: ...3 are indicated by the data bank register DTB Figure B 4 6 Example of Register Indirect Addressing with Base Index RW0 RW7 RW1 RW7 MOVW A RW1 RW7 This instruction reads data by register indirect addressing with a base index and stores it in A Before execution A 0 7 1 6 2 5 3 4 Memory space RW1 D 3 0 F 78D410H E E DTB 7 8 WR7 0 1 0 1 78D411H F F After execution A 2 5 3 4 F F E E RW1 D 3 0 F DTB 7 8...

Page 668: ...unconditional branch instructions Address bits 16 to 23 are indicated by the program counter bank register PCB Figure B 4 7 Example of Program Counter Relative Branch Addressing rel Register list rlst Specify a register to be pushed onto or popped from a stack Figure B 4 8 Configuration of the Register List BRA 10H This instruction causes an unconditional relative branch Before execution PC 3 C 2 ...

Page 669: ...on transfers memory data indicated by the SP to multiple word registers indicated by the register list SP 3 4 F A SP 3 4 F E RW0 RW0 0 2 0 1 RW1 RW1 RW2 RW2 RW3 RW3 RW4 RW4 0 4 0 3 RW5 RW5 RW6 RW6 RW7 RW7 Memory space Memory space SP 0 1 34FAH 0 1 34FAH 0 2 34FBH 0 2 34FBH 0 3 34FCH 0 3 34FCH 0 4 34FDH 0 4 34FDH 34FEH SP 34FEH Before execution After execution MOVW A A This instruction reads data b...

Page 670: ... Indirect specification branch addressing ear The address of the branch destination is the word data at the address indicated by ear Figure B 4 12 Example of Indirect Specification Branch Addressing ear JMP A This instruction causes an unconditional branch by accumulator indirect branch addressing Before execution PC 3 C 2 0 PCB 4 F Memory space A 6 6 7 7 3 B 2 0 4F3B20H Next instruction 4F3C20H 6...

Page 671: ...ated by eam Figure B 4 13 Example of Indirect Specification Branch Addressing eam JMP RW0 This instruction causes an unconditional branch by register indirect addressing Before execution PC 3 C 2 0 PCB 4 F Memory space RW0 3 B 2 0 4F3B20H Next instruction 4F3C20H 7 3 JMP RW0 After execution PC 3 B 2 0 PCB 4 F 4F3C21H 0 0 RW0 3 B 2 0 ...

Page 672: ...it bus the program fetches the instruction being executed in word increments Therefore intervening in data access increases the execution cycle count Similarly in the mode of fetching an instruction from memory connected to an 8 bit external bus the program fetches every byte of an instruction being executed Therefore intervening in data access increases the execution cycle count In CPU intermitte...

Page 673: ...ddressing Mode Code Operand a Register access count in each addressing mode Execution cycle count in each addressing mode 00 07 Ri Rwi RLi See the instruction list See the instruction list 08 0B RWj 2 1 0C 0F RWj 4 2 10 17 RWi disp8 2 1 18 1B RWi disp16 2 1 1C 1D 1E 1F RW0 RW7 RW1 RW7 PC disp16 addr16 4 4 2 1 2 2 0 0 a is used for cycle count and B correction value in B 8 F2MC 16LX Instruction Lis...

Page 674: ... Count Correction Values for Counting Execution Cycles Operand b byte c word d long Cycle count Access count Cycle count Access count Cycle count Access count Internal register 0 1 0 1 0 2 Internal memory Even address 0 1 0 1 0 2 Internal memory Odd address 0 1 2 2 4 4 External data bus 16 bit even address 1 1 1 1 2 2 External data bus 16 bit odd address 1 1 4 2 8 4 External data bus 8 bits 1 1 4 ...

Page 675: ...0 Register indirect 0 09 RW1 0A RW2 0B RW3 0C RW0 Register indirect with post increment 0 0D RW1 0E RW2 0F RW3 10 RW0 disp8 Register indirect with 8 bit displacement 1 11 RW1 disp8 12 RW2 disp8 13 RW3 disp8 14 RW4 disp8 15 RW5 disp8 16 RW6 disp8 17 RW7 disp8 18 RW0 disp16 Register indirect with 16 bit displacement 2 19 RW1 disp16 1A RW2 disp16 1B RW3 disp16 1C RW0 RW7 Register indirect with index ...

Page 676: ...al letters in items RG Indicates the number of times a register access is performed during instruction execution The number is used to calculate the correction value for CPU intermittent operation B Indicates the correction value used to calculate the actual number of cycles during instruction execution The actual number of cycles during instruction execution can be determined by adding the value ...

Page 677: ...tween read and write operations Table B 7 2 Explanation on Symbols in the Instruction List 1 2 Symbol Explanation A The bit length used varies depending on the 32 bit accumulator instruction Byte Low order 8 bits of byte AL Word 16 bits of word AL Long word 32 bits of AL and AH AH 16 high order bits of A AL 16 low order bits of A SP Stack pointer USP or SSP PC Program counter PCB program counter b...

Page 678: ...0FFH imm4 4 bit immediate data imm8 8 bit immediate data imm16 16 bit immediate data imm32 32 bit immediate data ext imm8 16 bit data obtained by sign extension of 8 bit immediate data disp8 8 bit displacement disp16 16 bit displacement bp Bit offset vct4 Vector number 0 to 15 vct8 Vector number 0 to 255 b Bit address rel PC relative branch ear Effective addressing code 00 to 07 eam Effective addr...

Page 679: ... A Ri X MOVX A ear 2 2 1 0 byte A ear X MOVX A eam 2 3 a 0 b byte A eam X MOVX A io 2 3 0 b byte A io X MOVX A imm8 2 2 0 0 byte A imm8 X MOVX A A 2 3 0 b byte A A X MOVX A RWi disp8 2 5 1 b byte A RWi disp8 X MOVX A RLi disp8 3 10 2 b byte A RLi disp8 X MOV dir A 2 3 0 b byte dir A MOV addr16 A 3 4 0 b byte addr16 A MOV Ri A 1 2 1 0 byte Ri A MOV ear A 2 2 1 0 byte ear A MOV eam A 2 3 a 0 b byte ...

Page 680: ... A 1 1 0 0 word SP A MOVW RWi A 1 2 1 0 word RWi A MOVW ear A 2 2 1 0 word ear A MOVW eam A 2 3 a 0 c word eam A MOVW io A 2 3 0 c word io A MOVW RWi disp8 A 2 5 1 c word RWi disp8 A MOVW RLi disp8 A 3 10 2 c word RLi disp8 A MOVW RWi ear 2 3 2 0 word RWi ear MOVW RWi eam 2 4 a 1 c word RWi eam MOVW ear RWi 2 4 2 0 word ear RWi MOVW eam RWi 2 5 a 1 c word eam RWi MOVW RWi imm16 3 2 1 0 word RWi im...

Page 681: ...B eam A 2 5 a 0 2 b byte eam eam A SUBC A 1 2 0 0 byte A AH AL C Z SUBC A ear 2 3 1 0 byte A A ear C Z SUBC A eam 2 4 a 0 b byte A A eam C Z SUBDC A 1 3 0 0 byte A AH AL C decimal Z ADDW A 1 2 0 0 word A AH AL ADDW A ear 2 3 1 0 word A A ear ADDW A eam 2 4 a 0 c word A A eam ADDW A imm16 3 2 0 0 word A A imm16 ADDW ear A 2 3 2 0 word ear ear A ADDW eam A 2 5 a 0 2 c word eam eam A ADDCW A ear 2 3 ...

Page 682: ... 2 5 a 0 2 c word eam eam 1 DECW ear 2 3 2 0 word ear ear 1 DECW eam 2 5 a 0 2 c word eam eam 1 INCL ear 2 7 4 0 long ear ear 1 INCL eam 2 9 a 0 2 d long eam eam 1 DECL ear 2 7 4 0 long ear ear 1 DECL eam 2 9 a 0 2 d long eam eam 1 Table B 8 5 11 Compare Instructions Byte Word Long Word Mnemonic RG B Operation LH AH I S T N Z V C RMW CMP A 1 1 0 0 byte AH AL CMP A ear 2 2 1 0 byte A ear CMP A eam ...

Page 683: ... 8 0 0 byte AH byte AL word A MULU A ear 2 9 1 0 byte A byte ear word A MULU A eam 2 10 0 b byte A byte eam word A MULUW A 1 11 0 0 word AH word AL Long A MULUW A ear 2 12 1 0 word A word ear Long A MULUW A eam 2 13 0 c word A word eam Long A 1 3 Division by 0 7 Overflow 15 Normal 2 4 Division by 0 8 Overflow 16 Normal 3 6 a Division by 0 9 a Overflow 19 a Normal 4 4 Division by 0 7 Overflow 22 No...

Page 684: ...e A byte ear word A MUL A eam 2 10 0 b byte A byte eam word A MULW A 2 11 0 0 word AH word AL Long A MULW A ear 2 12 1 0 word A word ear Long A MULW A eam 2 13 0 c word A word eam Long A 1 3 Division by 0 8 or 18 Overflow 18 Normal 2 4 Division by 0 11 or 22 Overflow 23 Normal 3 5 a Division by 0 12 a or 23 a Overflow 24 a Normal 4 When dividend is positive 4 Division by 0 12 or 30 Overflow 31 Nor...

Page 685: ...a 0 2 b byte eam eam xor A R NOT A 1 2 0 0 byte A not A R NOT ear 2 3 2 0 byte ear not ear R NOT eam 2 5 a 0 2 b byte eam not eam R ANDW A 1 2 0 0 word A AH and A R ANDW A imm16 3 2 0 0 word A A and imm16 R ANDW A ear 2 3 1 0 word A A and ear R ANDW A eam 2 4 a 0 c word A A and eam R ANDW ear A 2 3 2 0 word ear ear and A R ANDW eam A 2 5 a 0 2 c word eam eam and A R ORW A 1 2 0 0 word A AH or A R ...

Page 686: ...ear 2 6 2 0 long A A xor ear R XORL A eam 2 7 a 0 d long A A xor eam R Table B 8 10 6 Sign Inversion Instructions Byte Word Mnemonic RG B Operation LH AH I S T N Z V C RMW NEG A 1 2 0 0 byte A 0 A X NEG ear 2 3 2 0 byte ear 0 ear NEG eam 2 5 a 0 2 b byte eam 0 eam NEGW A 1 2 0 0 word A 0 A NEGW ear 2 3 2 0 word ear 0 ear NEGW eam 2 5 a 0 2 c word eam 0 eam Table B 8 11 1 Normalization Instruction ...

Page 687: ...te A Arithmetic right shift A 1 bit LSR A R0 2 1 1 0 byte A Logical right barrel shift A R0 LSL A R0 2 1 1 0 byte A Logical left barrel shift A R0 ASRW A 1 2 0 0 word A Arithmetic right shift A 1 bit LSRW A SHRW A 1 2 0 0 word A Logical right shift A 1 bit R LSLW A SHLW A 1 2 0 0 word A Logical left shift A 1 bit ASRW A R0 2 1 1 0 word A Arithmetic right barrel shift A R0 LSRW A R0 2 1 1 0 word A ...

Page 688: ...rel 2 1 0 0 Branch on C or Z 0 BRA rel 2 1 0 0 Unconditional branch JMP A 1 2 0 0 word PC A JMP addr16 3 3 0 0 word PC addr16 JMP ear 2 3 1 0 word PC ear JMP eam 2 4 a 0 c word PC eam JMPP ear 3 2 5 2 0 word PC ear PCB ear 2 JMPP eam 3 2 6 a 0 d word PC eam PCB eam 2 JMPP addr24 4 4 0 0 word PC ad24 0 15 PCB ad24 16 23 CALL ear 4 2 6 1 c word PC ear CALL eam 4 2 7 a 0 2 c word PC eam CALL addr16 5...

Page 689: ...errupt R S INT addr16 3 16 0 6 c Software interrupt R S INTP addr24 4 17 0 6 c Software interrupt R S INT9 1 20 0 8 c Software interrupt R S RETI 1 8 0 7 Return from interrupt LINK imm8 2 6 0 c Saves the old frame pointer in the stack upon entering the function then sets the new frame pointer and reserves the local pointer area UNLINK 1 5 0 c Recovers the old frame pointer from the stack upon exit...

Page 690: ...mm8 MOV ILM imm8 2 2 0 0 byte ILM imm8 MOVEA RWi ear 2 3 1 0 word RWi ear MOVEA RWi eam 2 2 a 1 0 word RWi eam MOVEA A ear 2 1 0 0 word A ear MOVEA A eam 2 1 a 0 0 word A eam ADDSP imm8 2 3 0 0 word SP SP ext imm8 ADDSP imm16 3 3 0 0 word SP SP imm16 MOV A brg1 2 1 0 0 byte A brg1 Z MOV brg2 A 2 1 0 0 byte brg2 A NOP 1 1 0 0 No operation ADB 1 1 0 0 Prefix code for AD space access DTB 1 1 0 0 Pref...

Page 691: ...ranch on dir bp b 0 BBC addr16 bp rel 5 1 0 b Branch on addr16 bp b 0 BBC io bp rel 4 2 0 b Branch on io bp b 0 BBS dir bp rel 4 1 0 b Branch on dir bp b 1 BBS addr16 bp rel 5 1 0 b Branch on addr16 bp b 1 BBS io bp rel 4 2 0 b Branch on io bp b 1 SBBS addr16 bp rel 5 3 0 2 b Branch on addr16 bp b 1 bit addr16 bp b 1 WBTS io bp 3 4 0 5 Waits until io bp b 1 WBTC io bp 3 4 0 5 Waits until io bp b 0...

Page 692: ...m 6 8 3 byte fill AH AL counter RW0 MOVSW MOVSWI 2 2 5 6 word transfer AH AL counter RW0 MOVSWD 2 2 5 6 word transfer AH AL counter RW0 SCWEQ SCWEQI 2 1 8 7 word search AH AL counter RW0 SCWEQD 2 1 8 7 word search AH AL counter RW0 FILSW FILSWI 2 6m 6 8 6 word fill AH AL counter RW0 1 5 when RW0 is 0 4 7 RW0 when the counter expires or 7n 5 when a match occurs 2 5 when RW0 is 0 otherwise 4 8 RW0 3...

Page 693: ... as the NOP instruction that ends in one byte is completed within the basic page An instruction such as the MOVS instruction that requires two bytes recognizes the existence of byte 2 when it references byte 1 and can check the following one byte by referencing the map for byte 2 Figure B 9 2 shows the correspondence between an actual instruction code and instruction map Basic page map Byte 1 Bit ...

Page 694: ... 2 byte instructions and ea instructions Actually there are multiple extended page maps for each type of instructions Some instructions do not contain byte 2 Length varies depending on the instruction Instruction code Byte 1 Byte 2 Operand Operand Basic page map XY Z Extended page map UV W Table B 9 1 Example of an Instruction Code Instruction Byte 1 from basic page map Byte 2 from extended page m...

Page 695: ...A SP MOVW io 16 RETP ea instruction 7 BV rel 7 SPB ADDSP 8 MULU A NOT A MOVW SP A MOVX A addr16 RET ea instruction 8 BNV rel 8 LINK imm8 ADDL A 32 ADDW A ADDW A 16 MOVW A dir MOVW A io INT vct8 ea instruction 9 MOVW A RWi MOVW RWi A MOVW RWi 16 MOV A RWi d8 MOVW RWi d8 A BT rel 9 UNLINK SUBL A 32 SUBW A SUBW A 16 MOVW dir A MOVW io A INT addr16 MOVEA RWi ea BNT rel A MOV RP 8 MOV ILM 8 CBNE A 8 re...

Page 696: ... F0 0 MOVB A io bp MOVB io bp A CLRB io bp SETB io bp BBC io bp rel BBS io bp rel WBTS io bp WBTC io bp 1 2 3 4 5 6 7 8 MOVB A dir bp MOVB A addr16 bp MOVB dir bp A MOVB addr16 bp A CLRB dir bp CLRB addr16 bp SETB dir bp SETB addr16 bp BBC dir bp rel BBC addr16 bp rel BBS dir bp rel BBS addr16 bp rel SBBS addr16 bp 9 A B C D E F ...

Page 697: ... E0 F0 0 MOVSI PCB PCB MOVSD MOVSWI MOVSWD SCEQI PCB SCEQD PCB SCWEQI PCB SCWEQD PCB FILSI PCB FILSI PCB 1 PCB DTB DTB DTB DTB DTB DTB DTB 2 PCB ADB ADB ADB ADB ADB ADB ADB 3 PCB SPB SPB SPB SPB SPB SPB SPB 4 DTB PCB 5 DTB DTB 6 DTB ADB 7 DTB SPB 8 ADB PCB 9 ADB DTB A ADB ADB B ADB SPB C SPB PCB D SPB DTB E SPB ADB F SPB SPB ...

Page 698: ...A MOV A RL1 d8 3 MOV A USB MOV USB A 4 MOV A DPR MOV DPR A MOVX A RL2 d8 MOV RL2 d8 A MOV A RL2 d8 5 MOV A A MOV AL AH 6 MOV A PCB MOV A A MOVX A RL3 d8 MOV RL3 d8 A MOV A RL3 d8 7 ROLC A ROLC A 8 MOVW RL0 d8 A MOVW A RL0 d8 MUL A 9 MULW A A MOVW RL1 d8 A MOVW A RL1 d8 DIVU A B C LSLW A R0 LSLL A R0 LSL A R0 MOVW RL2 d8 A MOVW A RL2 d8 D MOVW A A MOVW AL AH NRML A R0 E ASRW A R0 ASRL A R0 ASR A R0...

Page 699: ...MPL A RL3 CMPL A RW7 d8 ANDL A RL3 ANDL A RW7 d8 ORL A RL3 ORL A RW7 d8 XORL A RL3 XORL A RW7 d8 R7 8 rel RW7 d8 8 rel 8 ADDL A RW0 ADDL A RW0 d16 SUBL A RW0 SUBL A RW0 d16 RW0 16 rel RW0 d16 16 rel CMPL A RW0 CMPL A RW0 d16 ANDL A RW0 ANDL A RW0 d16 ORL A RW0 ORL A RW0 d16 XORL A RW0 XORL A RW0 d16 RW0 8 rel RW0 d16 8 rel 9 ADDL A RW1 ADDL A RW1 d16 SUBL A RW1 SUBL A RW1 d16 RW1 16 rel RW1 d16 16...

Page 700: ... INCL RW7 d8 DECL RL3 DECL RW7 d8 MOVL A RL3 MOVL A RW7 d8 MOVL RL3 A MOVL RW7 d8 A MOV R7 8 MOV RW7 d8 8 MOVEA A RW7 MOVEA A RW7 d8 8 JMPP RW0 JMPP RW0 d16 CALLP RW0 CALLP RW0 d16 INCL RW0 INCL RW0 d16 DECL RW0 DECL RW0 d16 MOVL A RW0 MOVL A RW0 d16 MOVL RW0 A MOVL RW0 d16 A MOV RW0 8 MOV RW0 d16 8 MOVEA A RW0 MOVEA A RW0 d16 9 JMPP RW1 JMPP RW1 d16 CALLP RW1 CALLP RW1 d16 INCL RW1 INCL RW1 d16 D...

Page 701: ... RW7 d8 MOV A R7 MOV A RW7 d8 MOV R7 A MOV RW7 d8 A MOVX A R7 MOVX A RW7 d8 XCH A R7 XCH A RW7 d8 8 ROLC RW0 ROLC RW0 d16 RORC RW0 RORC RW0 d16 INC RW0 INC RW0 d16 DEC RW0 DEC RW0 d16 MOV A RW0 MOV A RW0 d16 MOV RW0 A MOV RW0 d16 A MOVX A RW0 MOVX A RW0 d16 XCH A RW0 XCH A RW0 d16 9 ROLC RW1 ROLC RW1 d16 RORC RW1 RORC RW1 d16 INC RW1 INC RW1 d16 DEC RW1 DEC RW1 d16 MOV A RW1 MOV A RW1 d16 MOV RW1 ...

Page 702: ...7 INCW RW7 d8 DECW RW7 DECW RW7 d8 MOVW A RW7 MOVW A RW7 d8 MOVW RW7 A MOVW RW7 d8 A MOVW RW7 16 MOVW RW7 d8 16 XCHW A RW7 XCHW A RW7 d8 8 JMP RW0 JMP RW0 d16 CALL RW0 CALL RW0 d16 INCW RW0 INCW RW0 d16 DECW RW0 DECW RW0 d16 MOVW A RW0 MOVW A RW0 d16 MOVW RW0 A MOVW RW0 d16 A MOVW RW0 16 MOVW RW0 d16 16 XCHW A RW0 XCHW A RW0 d16 9 JMP RW1 JMP RW1 d16 CALL RW1 CALL RW1 d16 INCW RW1 INCW RW1 d16 DEC...

Page 703: ...RW7 d8 AND A R7 AND A RW7 d8 OR A R7 OR A RW7 d8 XOR A R7 XOR A RW7 d8 DBNZ R7 r DBNZ RW7 d8 r 8 ADD A RW0 ADD A RW0 d16 SUB A RW0 SUB A RW0 d16 ADDC A RW0 ADDC A RW0 d16 CMP A RW0 CMP A RW0 d16 AND A RW0 AND A RW0 d16 OR A RW0 OR A RW0 d16 XOR A RW0 XOR A RW0 d16 DBNZ RW0 r DBNZ R W0 d16 r 9 ADD A RW1 ADD A RW1 d16 SUB A RW1 SUB A RW1 d16 ADDC A RW1 ADDC A RW1 d16 CMP A RW1 CMP A RW1 d16 AND A RW...

Page 704: ...EG R7 NEG A RW7 d8 AND R7 A AND RW7 d8 A OR R7 A OR RW7 d8 A XOR R7 A XOR RW7 d8 A NOT R7 NOT RW7 d8 8 ADD RW0 A ADD RW0 d16 A SUB RW0 A SUB RW0 d16 A SUBC A RW0 SUBC A RW0 d16 NEG RW0 NEG A RW0 d16 AND RW0 A AND RW0 d16 A OR RW0 A OR RW0 d16 A XOR RW0 A XOR RW0 d16 A NOT RW0 NOT RW0 d16 9 ADD RW1 A ADD R RW1 d16 A SUB RW1 A SUB RW1 d16 A SUBC A RW1 SUBC A RW1 d16 NEG RW1 NEG A RW1 d16 AND RW1 A A...

Page 705: ...8 CMPW A RW7 CMPW A RW7 d8 ANDW A RW7 ANDW A RW7 d8 ORW A RW7 ORW A RW7 d8 XORW A RW7 XORW A RW7 d8 DWBNZ RW7 r DWBNZ RW7 d8 r 8 ADDW A RW0 ADDW A RW0 d16 SUBW A RW0 SUBW A RW0 d16 ADDCW A RW0 ADDCW A RW0 d16 CMPW A RW0 CMPW A RW0 d16 ANDW A RW0 ANDW A RW0 d16 ORW A RW0 ORW A RW0 d16 XORW A RW0 XORW A RW0 d16 DWBNZ RW0 r DWBNZ RW0 d16 r 9 ADDW A RW1 ADDW A RW1 d16 SUBW A RW1 SUBW A RW1 d16 ADDCW A...

Page 706: ...W A RW7 SUBCW A RW7 d8 NEGW RW7 NEGW RW7 d8 ANDW RW7 A ANDW RW7 d8 A ORW RW7 A ORW RW7 d8 A XORW RW7 A XORW RW7 d8 A NOTW RW7 NOTW RW7 d8 8 ADDW RW0 A ADDW RW0 d16 A SUBW RW0 A SUBW RW0 d16 A SUBCW A RW0 SUBCW A RW0 d16 NEGW RW0 NEGW RW0 d16 ANDW RW0 A ANDW RW0 d16 A ORW RW0 A ORW RW0 d16 A XORW RW0 A XORW RW0 d16 A NOTW RW0 NOTW RW0 d16 9 ADDW RW1 A ADDW RW1 d16 A SUBW RW1 A SUBW RW1 d16 A SUBCW ...

Page 707: ...7 MULW A RW7 d8 DIVU A R7 DIVU A RW7 d8 DIVUW A RW7 DIVUW A RW7 d8 DIV A R7 DIV A RW7 d8 DIVW A RW7 DIVW A RW7 d8 8 MULU A RW0 MULU A RW0 d16 MULUW A RW0 MULUW A RW0 d16 MUL A RW0 MUL A RW0 d16 MULW A RW0 MULW A RW0 d16 DIVU A RW0 DIVU A RW0 d16 DIVUW A RW0 DIVUW A RW0 d16 DIV A RW0 DIV A RW0 d16 DIVW A RW0 DIVW A RW0 d16 9 MULU A RW1 MULU A RW1 d16 MULUW A RW1 MULUW A RW1 d16 MUL A RW1 MUL A RW1 ...

Page 708: ... MOVEA RW3 RW7 d8 MOVEA RW4 RW7 MOVEA RW4 RW7 d8 MOVEA RW5 RW7 MOVEA RW5 RW7 d8 MOVEA RW6 RW7 MOVEA RW6 RW7 d8 MOVEA RW7 RW7 MOVEA RW7 RW7 d8 8 MOVEA RW0 RW0 MOVEA RW0 RW0 d16 MOVEA RW1 RW0 MOVEA RW1 RW0 d16 MOVEA RW2 RW0 MOVEA RW2 RW0 d16 MOVEA RW3 RW0 MOVEA RW3 RW0 d16 MOVEA RW4 RW0 MOVEA RW4 RW0 d16 MOVEA RW5 RW0 MOVEA RW5 RW0 d16 MOVEA RW6 RW0 MOVEA RW6 RW0 d16 MOVEA RW7 RW0 MOVEA RW7 RW0 d16 ...

Page 709: ...7 d8 MOV R4 R7 MOV R4 RW7 d8 MOV R5 R7 MOV R5 RW7 d8 MOV R6 R7 MOV R6 RW7 d8 MOV R7 R7 MOV R7 RW7 d8 8 MOV R0 RW0 MOV R0 RW0 d16 MOV R1 RW0 MOV R1 RW0 d16 MOV R2 RW0 MOV R2 RW0 d16 MOV R3 RW0 MOV R3 RW0 d16 MOV R4 RW0 MOV R4 RW0 d16 MOV R5 RW0 MOV R5 RW0 d16 MOV R6 RW0 MOV R6 RW0 d16 MOV R7 RW0 MOV R7 RW0 d16 9 MOV R0 RW1 MOV R0 RW1 d16 MOV R1 RW1 MOV R1 RW1 d16 MOV R2 RW1 MOV R2 RW1 d16 MOV R3 RW...

Page 710: ...VW RW3 RW7 MOVW RW3 RW7 d8 MOVW RW4 RW7 MOVW RW4 RW7 d8 MOVW RW5 RW7 MOVW RW5 RW7 d8 MOVW RW6 RW7 MOVW RW6 RW7 d8 MOVW RW7 RW7 MOVW RW7 RW7 d8 8 MOVW RW0 RW0 MOVW RW0 d16 MOVW RW1 RW0 MOVW RW1 RW0 d16 MOVW RW2 RW0 MOVW RW2 RW0 d16 MOVW RW3 RW0 MOVW RW3 RW0 d16 MOVW RW4 RW0 MOVW RW4 RW0 d16 MOVW RW5 RW0 MOVW RW5 RW0 d16 MOVW RW6 RW0 MOVW RW6 RW0 d16 MOVW RW7 RW0 MOVW RW7 RW0 d16 9 MOVW RW0 RW1 MOVW...

Page 711: ...8 R3 MOV R7 R4 MOV RW7 d8 R4 MOV R7 R5 MOV RW7 d8 R5 MOV R7 R6 MOV RW7 d8 R6 MOV R7 R7 MOV RW7 d8 R7 8 MOV RW0 R0 MOV RW0 d16 R0 MOV RW0 R1 MOV RW0 d16 R1 MOV RW0 R2 MOV RW0 d16 R2 MOV RW0 R3 MOV RW0 d16 R3 MOV RW0 R4 MOV RW0 d16 R4 MOV RW0 R5 MOV RW0 d16 R5 MOV RW0 R6 MOV RW0 d16 R6 MOV RW0 R7 MOV RW0 d16 R7 9 MOV RW1 R0 MOV RW1 d16 R0 MOV RW1 R1 MOV RW1 d16 R1 MOV RW1 R2 MOV RW1 d16 R2 MOV RW1 R...

Page 712: ... RW7 RW3 MOVW RW7 d8 RW3 MOVW RW7 RW4 MOVW RW7 d8 RW4 MOVW RW7 RW5 MOVW RW7 d8 RW5 MOVW RW7 RW6 MOVW RW7 d8 RW6 MOVW RW7 RW7 MOVW RW7 d8 RW7 8 MOVW RW0 RW0 MOVW RW0 d16 RW0 MOVW RW0 RW1 MOVW RW0 d16 RW1 MOVW RW0 RW2 MOVW RW0 d16 RW2 MOVW RW0 RW3 MOVW RW0 d16 RW3 MOVW RW0 RW4 MOVW RW0 d16 RW4 MOVW RW0 RW5 MOVW RW0 d16 RW5 MOVW RW0 RW6 MOVW RW0 d16 RW6 MOVW RW0 RW7 MOVW RW0 d16 RW7 9 MOVW RW1 RW0 MO...

Page 713: ...XCH R4 R7 XCH R4 RW7 d8 XCH R5 R7 XCH R5 RW7 d8 XCH R6 R7 XCH R6 RW7 d8 XCH R7 R7 XCH R7 RW7 d8 8 XCH R0 RW0 XCH R0 RW0 d16 XCH R1 RW0 XCH R1 RW0 d16 XCH R2 RW0 XCH R2 RW0 d16 XCH R3 RW0 XCH R3 RW0 d16 XCH R4 RW0 XCH R4 RW0 d16 XCH R5 RW0 XCH R5 RW0 d16 XCH R6 RW0 XCH R6 RW0 d16 XCH R7 RW0 XCH R7 RW0 d16 9 XCH R0 RW1 XCH R0 RW1 d16 XCH R1 RW1 XCH R1 RW1 d16 XCH R2 RW1 XCH R2 RW1 d16 XCH R3 RW1 XCH...

Page 714: ... RW3 RW7 XCHW RW3 RW7 d8 XCHW RW4 RW7 XCHW RW4 RW7 d8 XCHW RW5 RW7 XCHW RW5 RW7 d8 XCHW RW6 RW7 XCHW RW6 RW7 d8 XCHW RW7 RW7 XCHW RW7 RW7 d8 8 XCHW RW0 RW0 XCHW RW0 RW0 d16 XCHW RW1 RW0 XCHW RW1 RW0 d16 XCHW RW2 RW0 XCHW RW2 RW0 d16 XCHW RW3 RW0 XCHW RW3 RW0 d16 XCHW RW4 RW0 XCHW RW4 RW0 d16 XCHW RW5 RW0 XCHW RW5 RW0 d16 XCHW RW6 RW0 XCHW RW6 RW0 d16 XCHW RW7 RW0 XCHW RW7 RW0 d16 9 XCHW RW0 RW1 XC...

Page 715: ...696 APPENDIX ...

Page 716: ...697 INDEX INDEX The index follows on the next page This is listed in alphabetic order ...

Page 717: ...sage Notes on the 16 bit PPG Timer 276 16 bit Reload Register 16 bit Reload Register TMRD0 TMRD1 242 16 bit Reload Timer 16 bit Reload Timer Interrupts 243 16 bit Reload Timer Interrupts and EI2 OS 243 16 bit Reload Timer Interrupts and EI2 OS 232 16 bit Reload Timer Pins 235 16 bit Reload Timer Registers 236 16 bit Reload Timer Settings 244 Baud Rates determined using the Internal Timer 16 bit Re...

Page 718: ...ock Diagrams of the 8 10 bit A D Converter Pins 546 EI2 OS Function of the 8 10 bit A D Converter 556 Functions of the 8 10 bit A D Converter 542 Usage Notes on the 8 10 bit A D Converter 563 A D Data Register A D Data Register ADCR0 ADCR1 554 Access Space Bank Registers and Access Space 35 Accumulator Accumulator A 42 ADB Bank Registers PCB DTB USB SSB ADB 54 Bank Select Prefixes PCB DTB ADB SPB ...

Page 719: ...iagram of the 16 bit PPG Timer Pins 260 Block Diagram of the 16 bit Reload Timer 233 Block Diagram of the 16 bit Reload Timer Pins 235 Block Diagram of the 8 10 bit A D Converter 544 Block Diagram of the Clock Generation Block 80 Block Diagram of the Delayed Interrupt Generator Module 536 Block Diagram of the DTP external Interrupt Circuit 516 Block Diagram of the DTP external Interrupt Circuit Pi...

Page 720: ...mpare Clear Buffer Register CPCLRB 293 Compare Clear Register Compare Clear Register CPCLR 293 Compare Clear Register CPCR 388 Compare Control Register Compare Control Register Upper Byte OCS1 OCS3 OCS5 301 Compare Control Register Lower Byte OCS0 OCS2 OCS4 303 Condition Code Register Condition Code Register CCR Configuration 48 Connection Example of Connection for Serial Writing when Power Suppli...

Page 721: ...deletion 604 Deleting the data Sector deletion 605 Procedure for Writing Deleting the data to the Flash Memory 588 Procedure of Deleting a Sector 605 Deletion Operation When the Chip Sector Deletion Operation is Executed 595 When the Write Operation or Chip Sector Deletion Operation is Executed 597 598 Description Description of Instruction Presentation Items and Symbols 657 Descriptor Configurati...

Page 722: ...ternal Interrupt Circuit and EI2 OS 515 Multi pulse Generator EI2 OS Functions 396 Multi pulse Generator Interrupts and EI2 OS 396 Operation flow of the Extended Intelligent I O Service EI2 OS 145 Operation of the Extended Intelligent I O Service EI2 OS 140 Procedure for using the Extended Intelligent I O Service EI2 OS 146 Processing Specifications of Sample Program for Extended Intelligent I O S...

Page 723: ...peration 460 Flowchart of Timer Mode Operation 455 FMCS Control Status Register FMCS 590 FPT 64P M06 FPT 64P M06 Package Dimensions 12 FPT 64P M06 Pin Assignment 8 FPT 64P M09 FPT 64P M09 Package Dimensions 13 FPT 64P M09 Pin Assignment 9 Free run TImer Block Diagram of 16 bit Free run TImer 283 Free run Timer 16 bit Free run Timer 1 280 16 bit Free run Timer Interrupts 320 16 bit Free run Timer I...

Page 724: ...79 Input Capture 16 bit Input Capture 4 281 16 bit Input Capture Input Timing 338 16 bit Input Capture Interrupts 322 16 bit Input Capture Interrupts and EI2 OS 322 16 bit Input Capture Operation 337 Block Diagram of 16 bit Input Capture 284 Input Capture Registers 291 Usage Notes on the 16 bit Input Capture 350 Input Capture Control Status Register Input Capture Control Status Register Lower Byte...

Page 725: ...rol Registers Interrupt Causes and Interrupt Vectors interrupt Control Registers 117 Interrupt Level Mask Register Interrupt Level Mask Register ILM 51 Interrupt Mask Function Interrupt Mask Function 330 Interrupt Request Interrupt Request Generation 453 458 Interrupt Vectors Interrupt Causes and Interrupt Vectors interrupt Control Registers 117 Interrupt Vectors 116 Interrupts 16 bit Free run Tim...

Page 726: ...Measurement Result Data 456 Memory Map E2 PROM Memory Map 579 Memory Maps Memory Maps 31 Memory Space Memory Space 29 Microcontroller Connection of an Oscillator or an External Clock to the Microcontroller 87 Example of Minimum Connection with Flash Microcontroller Programmer when Power Supplied by User 622 Example of Minimum Connection with Flash Microcontroller Programmer when Power Supplied fro...

Page 727: ...37 Multi functional Timer Block Diagram of Multi functional Timer 282 Block Diagram of Multi functional Timer Pins 287 EI2 OS Function of the Multi functional Timer 323 Multi functional Timer Pins 286 Operation of Multi functional Timer 324 Multiple Interrupts Multiple Interrupts 133 Multiplier Selection of a PLL Clock Multiplier 84 Multi pulse Multi pulse Interrupts 394 Multi pulse Generator 16 b...

Page 728: ...g Diagram OPS2 to OPS0 000B 402 OPDR Register Write Timing Diagram OPS2 to OPS0 001B 010B 011B 100B 101B 110B 111B 404 Signal Flow Diagram for Position Detection by Setting OPS2 to OPS0 010B or 110B 403 Signal Flow Diagram for Reload Timer 0 and Position Detection by Setting OPS2 to OPS0 011B or 111B 403 Signal Flow Diagram for Reload Timer 0 or Position Detection by Setting OPS2 to OPS0 100B or 1...

Page 729: ...Timer Underflow DTCR0 DTCR1 DTCR2 TMD2 to TMD0 010B 342 Output Waveform OPTx Output Waveform Timing Diagram WTS1 WTS0 00B 398 Overlap Making Non overlap Signals by using PPG in Inverted Polarity DTCR0 DTCR1 DTCR2 TMD2 to TMD0 111B 346 Making Non overlap Signals by using PPG in Normal Polarity DTCR0 DTCR1 DTCR2 TMD2 to TMD0 111B 345 Making Non overlap Signals by using RT1 RT3 RT5 in Inverted Polari...

Page 730: ... 193 Port 5 Registers 194 Port 6 Block Diagram of Port 6 Pins 199 Functions of Port 6 Registers 200 Operation of Port 6 201 Port 6 Configuration 198 Port 6 Pins 198 Port 6 Registers 199 Position Signal Flow Diagram for Reload Timer 0 or Position Detection by Setting OPS2 to OPS0 100B or 101B 404 Position Detection Operation of Position Detection 399 Signal Flow Diagram for Position Detection by Se...

Page 731: ...Sample Program for the 16 bit PPG Timer 277 Usage Notes on the 16 bit PPG Timer 276 Prefix Consecutive Prefix Codes 63 Prefix Codes 57 Prefix Codes and Interrupt hold Suppression Instructions 62 Processing Time Hardware Interrupt Processing Time 135 Processing Time one transfer time of the Extended Intelligent I O Service EI2 OS 147 Processor Status Processor Status PS Configuration 47 Product Lin...

Page 732: ... Configuration 48 Control Status Register FMCS 590 Delayed Interrupt Generator Module Register DIRR 537 Direct Page Register DPR 53 Division Rate Control Register DIV0 DIV1 444 DTP interrupt Cause Register EIRR 521 DTP interrupt Enable Register ENIR 522 Input Capture Control Status Register Lower Byte ICSL23 307 Input Capture Control Status Register Lower Byte PICSL01 311 Input Capture Control Sta...

Page 733: ...OS Function of the 16 bit Reload Timer 243 Overview of the 16 bit Reload Timer 230 Signal Flow Diagram for Reload Timer 0 and Position Detection by Setting OPS2 to OPS0 011B or 111B 403 Signal Flow Diagram for Reload Timer 0 or Position Detection by Setting OPS2 to OPS0 100B or 101B 404 Signal Flow Diagram for Reload Timer 0 Underflow by Setting OPS2 to OPS0 001B 402 Timing Generated by Reload Tim...

Page 734: ...mple Programs Sample Programs for Interrupt Processing 152 SCR Serial Control Register SCR0 SCR1 476 Sector Procedure of Deleting a Sector 605 Restarting the Sector Deletion 608 Sector Configuration 589 Temporarily Stopping the Sector Deletion 607 When the Sector Deletion Temporary Stop is Executed 595 597 Sector Deletion Restarting the Sector Deletion 608 Temporarily Stopping the Sector Deletion ...

Page 735: ...ations at the Start of Interrupt Processing 150 Stack Operations on Return from Interrupt Processing 150 Stack Selection 45 Storage of Multi byte Data in a Stack 38 Stack Pointer System Stack Pointer SSP 46 User Stack Pointer USP 46 Standard Configuration Standard Configuration for Fujitsu Standard Serial On board Writing 616 Standby Mode Notes on Standby Mode 110 Operating Status during Standby M...

Page 736: ...42 TMRR 16 bit Timer Registers TMRR0 TMRR1 TMRR2 313 Transfer Operation of Data Transfer of Output Data Register 407 transfer Processing Time one transfer time of the Extended Intelligent I O Service EI2 OS 147 Transition Clock Mode Transition 84 Transmission Interrupt Transmission Interrupt Heneration and Flag Set Timing 489 Trigger Gate Trigger PPG channel 0 only 275 U UART Block Diagram of UART...

Page 737: ...es on the Waveform Generator 350 Waveform Generator 281 Waveform Generator Interrupts 322 Waveform Generator Interrupts and EI2 OS 323 Waveform Generator Registers 292 Waveform Sequencer Block Diagram of Waveform Sequencer 360 Function of Waveform Sequencer 356 Usage Notes on the Waveform Sequencer 429 WDTC Watchdog Timer Control Register WDTC 222 Write Detailed Explanation on the Flash Memory Wri...

Page 738: ...ITSU MICROELECTRONICS CONTROLLER MANUAL F2MC 16LX 16 BIT MICROCONTROLLER MB90460 465 Series HARDWARE MANUAL August 2008 the fourth edition Published FUJITSU MICROELECTRONICS LIMITED Edited Business Media Promotion Dept ...

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