
380
CHAPTER 15 MULTI-PULSE GENERATOR
15.4.3
Output Data Buffer Register (OPDBR)
The Output Data Buffer Register is composed of twelve registers (OPDBRB to
OPDBR0). The value of the OPDBRx register specified by the BNKF, RDA2 to RDA0 bits
is loaded into the OPDR register at the rising edge of the write signal generated by the
Data Write Control Unit.
■
Output Data Buffer Upper Register (OPDBR)
Figure 15.4-6 Output Data Buffer Upper Register (OPDBR)
Addre
ss b
it 15
14
1
3
12
11
10
9
8
Initi
a
l v
a
l
u
e
00
3
FF7
H
to 00
3
FE1
H
BNKF
RDA2
RDA1
RDA0
OP51
OP50
OP41
OP40
00000000
B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
OP41 OP40
OPT4 output waveform
s
election bit
s
0
0
S
etting for OPT4 pin to o
u
tp
u
t “L” level.
0
1
S
etting for OPT4 pin to o
u
tp
u
t the o
u
tp
u
t of
the PPG timer.
1
0
S
etting for OPT4 pin to o
u
tp
u
t the inverted
o
u
tp
u
t of the PPG timer.
1
1
S
etting for OPT4 pin to o
u
tp
u
t “H” level.
OP51 OP50
OPT5 output waveform
s
election bit
s
0
0
S
etting for OPT5 pin to o
u
tp
u
t “L” level.
0
1
S
etting for OPT5 pin to o
u
tp
u
t the o
u
tp
u
t of
the PPG timer.
1
0
S
etting for OPT5 pin to o
u
tp
u
t the inverted
o
u
tp
u
t of the PPG timer.
1
1
S
etting for OPT5 pin to o
u
tp
u
t “H” level.
BNKF RDA2 RDA1 RDA0
OPDBR re
g
i
s
ter
s
election bit
s
0
0
0
0
S
et OPDBR0
as
next to
b
e lo
a
ded to OPDR.
0
0
0
1
S
et OPDBR1
as
next to
b
e lo
a
ded to OPDR.
0
0
1
0
S
et OPDBR2
as
next to
b
e lo
a
ded to OPDR.
0
0
1
1
S
et OPDBR
3
as
next to
b
e lo
a
ded to OPDR.
0
1
0
0
S
et OPDBR4
as
next to
b
e lo
a
ded to OPDR.
0
1
0
1
S
et OPDBR5
as
next to
b
e lo
a
ded to OPDR.
0
1
1
0
S
et OPDBR6
as
next to
b
e lo
a
ded to OPDR.
0
1
1
1
S
et OPDBR7
as
next to
b
e lo
a
ded to OPDR.
1
0
0
0
S
et OPDBR
8
as
next to
b
e lo
a
ded to OPDR.
1
0
0
1
S
et OPDBR9
as
next to
b
e lo
a
ded to OPDR.
1
0
1
0
S
et OPDBRA
as
next to
b
e lo
a
ded to OPDR.
1
0
1
1
S
et OPDBRB
as
next to
b
e lo
a
ded to OPDR.
Prohi
b
ited.
X :
Indetermin
a
te
R/W : Re
a
d
ab
le
a
nd writ
ab
le
: Initi
a
l v
a
l
u
e
—
: Not
us
ed
Other v
a
l
u
e
s
Summary of Contents for MB90460 Series
Page 1: ...The following document contains information on Cypress products ...
Page 3: ......
Page 5: ......
Page 9: ...iv ...
Page 41: ...22 CHAPTER 1 OVERVIEW ...
Page 45: ...26 CHAPTER 2 NOTES ON HANDLING DEVICES ...
Page 83: ...64 CHAPTER 3 CPU ...
Page 95: ...76 CHAPTER 4 RESET ...
Page 107: ...88 CHAPTER 5 CLOCK ...
Page 131: ...112 CHAPTER 6 LOW POWER CONSUMPTION MODE ...
Page 175: ...156 CHAPTER 7 INTERRUPT ...
Page 181: ...162 CHAPTER 8 MODE SETTING ...
Page 223: ...204 CHAPTER 9 I O PORT ...
Page 237: ...218 CHAPTER 10 TIME BASE TIMER ...
Page 247: ...228 CHAPTER 11 WATCHDOG TIMER ...
Page 275: ...256 CHAPTER 12 16 BIT RELOAD TIMER ...
Page 373: ...354 CHAPTER 14 MULTI FUNCTIONAL TIMER ...
Page 485: ...466 CHAPTER 16 PWC Timer ...
Page 531: ...512 CHAPTER 17 UART ...
Page 559: ...540 CHAPTER 19 DELAYED INTERRUPT GENERATOR MODULE ...
Page 589: ...570 CHAPTER 20 8 10 BIT A D CONVERTER ...
Page 601: ...582 CHAPTER 21 ROM CORRECTION FUNCTION ...
Page 633: ...614 CHAPTER 23 512K 1024K BIT FLASH MEMORY ...
Page 645: ...626 CHAPTER 24 EXAMPLE OF F2 MC 16LX MB90F462 F462A F463A CONNECTION FOR SERIAL WRITING ...
Page 715: ...696 APPENDIX ...
Page 716: ...697 INDEX INDEX The index follows on the next page This is listed in alphabetic order ...
Page 739: ......