Fujitsu MB90460 Series, Hardware Manual, Page: 410 / 739

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CHAPTER 15 MULTI-PULSE GENERATOR
Table 15.4-9 Timer Control Status Register (TCSR)
Bit name Function
bit7
TCLR:
Timer clear bit
•
The read value is always “0”.
•
Writing “1” to this bit initialize the counter to “0000
H
”.
•
Writing “0” has no effect.
bit6
MODE:
Timer reset
condition bit
•
This bit is used to set the reset condition for the 16-bit timer.
•
When it is “0”, 16-bit timer is reset by the write timing signal.
•
When it is “1”, 16-bit timer is reset by the position detection signal.
(Note)
Reset of the counter value is done at the changing point of the count value.
bit5
ICLR:
Compare clear
interrupt request
flag bit
•
This bit is an interrupt request flag for compare clear.
•
When the compare clear register and 16-bit free-run timer value are matched, the
counter is cleared and this bit becomes “1”.
•
Interrupt is generated when the interrupt request enable bit (bit12: ICRE) is set to
“1”.
•
Writing “0” clears this bit.
•
Writing “1” has no effect.
•
In read-modify-write operation, “1” is always read.
bit4
ICRE:
Compare clear
interrupt request
enable bit
•
This is the interrupt request enable bit for the compare clear.
•
When this bit is “1” and the interrupt flag (bit13: ICLR) is set to “1”, an interrupt
is generated.
bit3
TMEN:
Timer enable bit
•
This bit is used to enable/disable the counting of the 16-bit timer.
•
Writing “1” to this bit enables the counting of the 16-bit timer.
•
Writing “0” to this bit disables the counting of the 16-bit timer.
(Note)
When the 16-bit timer is disable, the output compare operation is also disabled.
bit2
to
bit0
CLK2 to CLK0:
Clock frequency
selection bit
•
These bits are used to select count clock for the 16-bit free-run timer.
(Note)
It is recommend to change these bits when the timer is in stop state because the
clock is changed as soon as these bits are updated.