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CHAPTER 3 CPU
3.8
General-purpose Registers
The general-purpose registers are a memory block allocated in RAM at 000180
H
to
00037F
H
as banks, each of which consists of eight 16-bit segments.
The general-purpose registers can be used as general-purpose 8-bit registers (byte
registers R0 to R7), 16-bit registers (word registers RW0 to RW7) or 32-bit registers
(long-word registers RL0 to RL7).
General-purpose registers can access RAM with a short instruction at high speed.
Since general-purpose registers are blocked into register banks, protection of register
contents and division into function units can readily be performed. When a general-
purpose register is used as a long-word register, it can be used as a linear pointer that
directly accesses the entire space.
■
Configuration of a General-purpose Register
All general-purpose registers exist in RAM at 000180
H
to 00037F
H
and are configured as 32 banks. The
register bank pointer (RP) specifies the bank that is to be used for a general-purpose register. The RP
points to the bank currently being used.
The RP determines the first address of each bank with the following formula:
Address of first general-purpose register = 000180
H
+ RP x 10
H
Figure 3.8-1 shows the location and
configuration of the general-purpose register banks in the memory space.
Figure 3.8-1 Location and Configuration of the General-purpose Register Banks in the Memory Space
Note:
The register bank pointer (RP) is initialized to 00
H
after a reset.
Built-in RAM
Register bank 31
Register bank 30
Register bank 21
Register bank 20
Register bank 19
Register bank 2
Register bank 1
Register bank 0
Conversion formula [000180
H
+ RP x 10
H
]
Byte address
Byte address
R0 to R7:
RW0 to RW7:
RL0 to RL3:
MSB:
LSB:
Byte registers
Word registers
Long-word registers
Most Significant Bit
Least Significant Bit
Summary of Contents for MB90460 Series
Page 1: ...The following document contains information on Cypress products ...
Page 3: ......
Page 5: ......
Page 9: ...iv ...
Page 41: ...22 CHAPTER 1 OVERVIEW ...
Page 45: ...26 CHAPTER 2 NOTES ON HANDLING DEVICES ...
Page 83: ...64 CHAPTER 3 CPU ...
Page 95: ...76 CHAPTER 4 RESET ...
Page 107: ...88 CHAPTER 5 CLOCK ...
Page 131: ...112 CHAPTER 6 LOW POWER CONSUMPTION MODE ...
Page 175: ...156 CHAPTER 7 INTERRUPT ...
Page 181: ...162 CHAPTER 8 MODE SETTING ...
Page 223: ...204 CHAPTER 9 I O PORT ...
Page 237: ...218 CHAPTER 10 TIME BASE TIMER ...
Page 247: ...228 CHAPTER 11 WATCHDOG TIMER ...
Page 275: ...256 CHAPTER 12 16 BIT RELOAD TIMER ...
Page 373: ...354 CHAPTER 14 MULTI FUNCTIONAL TIMER ...
Page 485: ...466 CHAPTER 16 PWC Timer ...
Page 531: ...512 CHAPTER 17 UART ...
Page 559: ...540 CHAPTER 19 DELAYED INTERRUPT GENERATOR MODULE ...
Page 589: ...570 CHAPTER 20 8 10 BIT A D CONVERTER ...
Page 601: ...582 CHAPTER 21 ROM CORRECTION FUNCTION ...
Page 633: ...614 CHAPTER 23 512K 1024K BIT FLASH MEMORY ...
Page 645: ...626 CHAPTER 24 EXAMPLE OF F2 MC 16LX MB90F462 F462A F463A CONNECTION FOR SERIAL WRITING ...
Page 715: ...696 APPENDIX ...
Page 716: ...697 INDEX INDEX The index follows on the next page This is listed in alphabetic order ...
Page 739: ......