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CHAPTER 15 MULTI-PULSE GENERATOR
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16-bit Timer
The 16-bit timer is used to act as an interval timer for motor speed checking and abnormal detection timer
when control DC sensorless motor. The detail is shown in Figure 15.2-3.
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Comparison Circuit
The Comparison Circuit is used to compare the RDA2 to RDA0 bits of the Output Data Register (OPDR:
RDA2 to RDA0) with the CPD2 to CPD0 bits of the Input Control Register (IPCR: CPD2 to CPD0) for
motor direction change. A compare match interrupt is generated when a match is happened.
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Data Write Control Unit
The Data Write Control Unit is used to generate the write signal (WTO) for transferring data from the
Output Data Buffer Register (OPDBR) to Output Data Register (OPDR). The detail is shown in Figure
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Decoder
The Decoder is used to decode the bit15 to bit12 of Output Data Register (OPDR: BNKF, RDA2 to RDA0)
to select which Output Data Buffer Register (OPDBRB to OPDBR0) is loaded into Output Data Register.
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DTTI1 Control
The DTTI1 Control is used to stop the Multi-pulse Generator output in case of emergency, that is triggered
by level "0" of DTTI1 input.
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Noise Filter
The Noise Filter is used to filter out the noise of the input signal in which there are 4 kind of sampling
clock for selection.
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Output Control Unit
The Output Control Unit is used to enable/disable PPG signal to the Multi-pulse Generator Outputs (OPT5
to OPT0).
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Position Detect Circuit
The Position Detect Circuit is used to detect the edge/level of the position input (SNI2 to SNI0). The detail
is shown in Figure 15.2-5.
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SYN Circuit
The SYN Circuit is used to synchronize the OPT5 to OPT0 outputs with the PPG signal.
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Noise Cancellation Control Register (NCCR)
The Noise Cancellation Control Register (NCCR) is used to select one of four sampling clock for the Noise
Filter.
Summary of Contents for MB90460 Series
Page 1: ...The following document contains information on Cypress products ...
Page 3: ......
Page 5: ......
Page 9: ...iv ...
Page 41: ...22 CHAPTER 1 OVERVIEW ...
Page 45: ...26 CHAPTER 2 NOTES ON HANDLING DEVICES ...
Page 83: ...64 CHAPTER 3 CPU ...
Page 95: ...76 CHAPTER 4 RESET ...
Page 107: ...88 CHAPTER 5 CLOCK ...
Page 131: ...112 CHAPTER 6 LOW POWER CONSUMPTION MODE ...
Page 175: ...156 CHAPTER 7 INTERRUPT ...
Page 181: ...162 CHAPTER 8 MODE SETTING ...
Page 223: ...204 CHAPTER 9 I O PORT ...
Page 237: ...218 CHAPTER 10 TIME BASE TIMER ...
Page 247: ...228 CHAPTER 11 WATCHDOG TIMER ...
Page 275: ...256 CHAPTER 12 16 BIT RELOAD TIMER ...
Page 373: ...354 CHAPTER 14 MULTI FUNCTIONAL TIMER ...
Page 485: ...466 CHAPTER 16 PWC Timer ...
Page 531: ...512 CHAPTER 17 UART ...
Page 559: ...540 CHAPTER 19 DELAYED INTERRUPT GENERATOR MODULE ...
Page 589: ...570 CHAPTER 20 8 10 BIT A D CONVERTER ...
Page 601: ...582 CHAPTER 21 ROM CORRECTION FUNCTION ...
Page 633: ...614 CHAPTER 23 512K 1024K BIT FLASH MEMORY ...
Page 645: ...626 CHAPTER 24 EXAMPLE OF F2 MC 16LX MB90F462 F462A F463A CONNECTION FOR SERIAL WRITING ...
Page 715: ...696 APPENDIX ...
Page 716: ...697 INDEX INDEX The index follows on the next page This is listed in alphabetic order ...
Page 739: ......