Fujitsu MB90460 Series, Hardware Manual, Page: 397 / 739

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CHAPTER 15 MULTI-PULSE GENERATOR
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Output Data Lower Register (OPDR)
Figure 15.4-5 Output Data Lower Register (OPDR)
Address bit 7 6 5 4 3 2 1 0 Initial value
003FF8
H
OP31 OP30 OP21 OP20 OP11 OP10 OP01 OP00 XXXXXXXX
B
R R R R R R R R
OP01 OP00 OPT0 output waveform selection bits
0 0 Pin OPT0 outputs “ L ” level.
0 1
Pin OPT0 outputs the output of the PPG
timer.
1 0
Pin OPT0 outputs the inverted output of
the PPG timer.
1 1
Pin OPT0 outputs “ H ” level.
OP11 OP10 OPT1 output waveform selection bits
0 0 Pin OPT1 outputs “ L ” level.
0 1
Pin OPT1 outputs the output of the PPG
timer.
1 0
Pin OPT1 outputs the inverted output of
the PPG timer.
1 1
Pin OPT1 outputs “ H ” level.
OP21 OP20 OPT2 output waveform selection bits
0 0 Pin OPT2 outputs “ L ” level.
0 1
Pin OPT2 outputs the output of the PPG
timer.
1 0
Pin OPT2 outputs the inverted output of
the PPG timer.
1 1
Pin OPT2 outputs “ H ” level.
OP31 OP30 OPT3 output waveform selection bits
0 0 Pin OPT3 outputs “ L ” level.
0 1
Pin OPT3 outputs the output of the PPG
timer.
1 0
Pin OPT3 outputs the inverted output of
the PPG timer.
1 1
Pin OPT3 outputs “ H ” level.
X : Indeterminate
R/W : Readable and writable
: Initial value
— : Not used