Fujitsu MB90460 Series, Hardware Manual, Page: 317 / 739

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CHAPTER 14 MULTI-FUNCTIONAL TIMER
Table 14.4-2 Timer control status register (TCCSL)
Bit name Function
bit7 Unused bit
•
The read value is indeterminate.
•
Writing to this bit has no effect on the operation.
bit6
BFE:
Compare clear
buffer enable bit
•
This bit is used to enable compare clear buffer.
•
Writing “0” disables compare clear buffer. Directly write in compare clear register is
possible.
•
Writing “1” enables compare clear buffer. Data written in compare clear buffer register
will be held and transfer to compare clear register when the count value of 16-bit free-
run timer is detected as zero.
bit5
STOP:
Timer enable bit
•
This bit is used to stop/start the counting of the 16-bit free-run timer.
•
Writing “1” stops the counting of the 16-bit free-run timer.
•
Writing “0” starts the counting of the 16-bit free-run timer.
(Note)
When the 16-bit free-run timer is stopped, the output compare operation will also be
stopped.
bit4
MODE:
Timer counting
mode bit
•
This bit is used to select the count mode of the 16-bit free-run timer.
•
Writing “0” selects up-count mode. Timer counts up until counter value matches with
compare clear register and reset to “0000
H
” and then counts up again.
•
Writing “1” selects up-down count mode.
In up-down count mode, whenever zero in the timer data register is detected, the timer
counting direction will always be reseted to up-counting.
The timer will reverse its counting direction whenever the timer value matches with
compare clear register.
•
This bit can be written at any time whether the timer is operating or stopped. The value
written to this bit is buffered and the count mode will be changed when timer value is
“0000
H
”.
(Note)
Because the timer will reverse its counting direction when compare-match is detected in
up-down count mode (MODE = 1), it should be careful to set the compare clear register
and timer data register when the timer is being counted down.
bit3
SCLR:
Timer clear bit
•
This bit is used to initialize the 16-bit free-run timer to “0000
H
”.
•
Writing “1” initializes 16-bit free-run timer to “0000
H
” at the next count clock.
•
Writing “0” will clear the bit SCLR if it is “1”.
•
Read value is always “0”.
(Note)
•
This bit cannot be used to initialize the timer when timer stops (STOP=1). Writing
“0000
H
” to timer data register (TCDT) can initialize the timer.
•
Writing “1” will not generate zero detect interrupt
.
•
This bit will be cleared by hardware after the timer is initialized to “0000”. If “0” is written to
the bit before timer initialization, the bit is cleared and the timer did not initi
•
Even after "1" is written, the counter value is not initialized if "0" is written to this bit
before the next count clock.
bit2
to
bit0
CLK2 to CLK0:
Clock frequency
selection bit
•
This bit is used to select count clock for the 16-bit free-run timer.
•
The count clock is changed immediately after these bits are set. So change them while
the output compare and input capture units are stopped.