Fujitsu MB90460 Series, Hardware Manual, Page: 389 / 739

370
CHAPTER 15 MULTI-PULSE GENERATOR
(Continued)
(Continued)
Addresses:
Read/Write
Initial Value
15
14
13 12 11
10
9
8
OPDBRB to
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Output Data Buffer Registers (Upper)
Addresses:
Read/Write
Initial Value
7
6
5
4
3
2 1
0
OPDBRB to
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Output Data Buffer Registers (Lower)
Address: 00008D
H
Read/Write
Initial Value
15
14
13
12
11
10
9
8
IPCUR
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Input Control Register (Upper)
Address: 00008C
H
Read/Write
Initial Value
7
6
5 4
3
2 1
0
IPCLR
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Input Control Register (Lower)
003FF7
H
to E1
H
003FF6
H
to E0
H
_
RDA0 OP51 OP50 OP41 OP40 RDA1 RDA2
OP31 OP30 OP21 OP20 OP11 OP10 OP01 OP00
WTS1 CPIF CPIE CPD2 CPD1 CPD0 CMPE
CPE1 CPE0 SNC2 SNC1 SNC0 SEE2 SEE1 SEE0
BNKF
WTS0
(Odd Addresses)
(Even Addresses)
bit
bit
bit
bit
OPDBR0
OPDBR0