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CHAPTER 14 MULTI-FUNCTIONAL TIMER
Table 14.4-8 Input Capture Control Status Register (PICSL01)
Bit name
Function
bit7
ICP1:
Interrupt request
flag bit
(Input capture 1)
•
This bit is used as interrupt request flag for input capture 1.
•
“1” is set to this bit upon detection of a valid edge of an external input pin.
•
While the interrupt enable bit (ICE1) is set, an interrupt can be generated upon
detection of a valid edge.
•
Writing “0” will clear this bit.
•
Writing “1” has no effect.
•
In read-modify-write operation, “1” is always read.
bit6
ICP0:
Interrupt request
flag bit
(Input capture 0)
•
This bit is used as interrupt request flag for input capture 0.
•
“1” is set to this bit upon detection of a valid edge of an external input pin.
•
While the interrupt enable bit (ICE0) is set, an interrupt can be generated upon
detection of a valid edge.
•
Writing “0” will clear this bit.
•
Writing “1” has no effect.
•
In read-modify-write operation, “1” is always read.
bit5
ICE1:
Interrupt request
enable bit
(Input capture 1)
•
This bit is used to enable input capture interrupt request for input capture 1.
•
While “1” is written to this bit, an input capture interrupt is generated when the
interrupt flag (ICP1) is set.
bit4
ICE0:
Interrupt request
enable bit
(Input capture 0)
•
This bit is used to enable input capture interrupt request for input capture 0.
•
While “1” is written to this bit, an input capture interrupt is generated when the
interrupt flag (ICP0) is set.
bit3,
bit2
EG11, EG10:
Edge selection
bit
(Input capture 1)
•
These bits are used to specify the valid edge polarity of an external input for input
capture 1.
•
These bits are also used to enable input capture operation.
bit1,
bit0
EG01, EG00:
Edge selection
bit
(Input capture 0)
•
These bits are used to specify the valid edge polarity of an external input for input
capture 0.
•
These bits are also used to enable input capture operation.
Summary of Contents for MB90460 Series
Page 1: ...The following document contains information on Cypress products ...
Page 3: ......
Page 5: ......
Page 9: ...iv ...
Page 41: ...22 CHAPTER 1 OVERVIEW ...
Page 45: ...26 CHAPTER 2 NOTES ON HANDLING DEVICES ...
Page 83: ...64 CHAPTER 3 CPU ...
Page 95: ...76 CHAPTER 4 RESET ...
Page 107: ...88 CHAPTER 5 CLOCK ...
Page 131: ...112 CHAPTER 6 LOW POWER CONSUMPTION MODE ...
Page 175: ...156 CHAPTER 7 INTERRUPT ...
Page 181: ...162 CHAPTER 8 MODE SETTING ...
Page 223: ...204 CHAPTER 9 I O PORT ...
Page 237: ...218 CHAPTER 10 TIME BASE TIMER ...
Page 247: ...228 CHAPTER 11 WATCHDOG TIMER ...
Page 275: ...256 CHAPTER 12 16 BIT RELOAD TIMER ...
Page 373: ...354 CHAPTER 14 MULTI FUNCTIONAL TIMER ...
Page 485: ...466 CHAPTER 16 PWC Timer ...
Page 531: ...512 CHAPTER 17 UART ...
Page 559: ...540 CHAPTER 19 DELAYED INTERRUPT GENERATOR MODULE ...
Page 589: ...570 CHAPTER 20 8 10 BIT A D CONVERTER ...
Page 601: ...582 CHAPTER 21 ROM CORRECTION FUNCTION ...
Page 633: ...614 CHAPTER 23 512K 1024K BIT FLASH MEMORY ...
Page 645: ...626 CHAPTER 24 EXAMPLE OF F2 MC 16LX MB90F462 F462A F463A CONNECTION FOR SERIAL WRITING ...
Page 715: ...696 APPENDIX ...
Page 716: ...697 INDEX INDEX The index follows on the next page This is listed in alphabetic order ...
Page 739: ......