Fujitsu MB90460 Series, Hardware Manual, Page: 56 / 739

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CHAPTER 3 CPU
3.5 Memory Location of Multi-byte Data
Multi-byte data is written to memory sequentially from the lower address. If multi-byte
data is 32-bit data, the lower 16 bits are transferred followed by the upper 16 bits.
If a reset signal is input immediately after the low-order data is written, the high-order
data may not be written.
■
Storage of Multi-byte Data in RAM
Figure 3.5-1 shows the data configuration of multi-byte data in memory. The lower 8 bits of the data is
located at address n, and subsequent data is located at address n + 1, address n + 2, address n + 3 and so on,
in this sequence.
Figure 3.5-1 Storage of Multi-byte Data in RAM
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Storage of Multi-byte Operand
Figure 3.5-2 shows the configuration of a multi-byte operand in memory.
Figure 3.5-2 Storage of a Multi-byte Operand
01010101
B
11001100
B
11111111
B
00010100
B
H
L
Address ‘n’
01010101
B
11001100
B
11111111
B
00010100
B
MSB LSB
12
H
34
H
56
H
63
H
H
L
Address ‘n’
JMPP 12 34 56H
JMPP 123456H