Fujitsu MB90460 Series, Hardware Manual, Page: 205 / 739

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CHAPTER 9 I/O PORT
9.6.2 Operation of Port 3
This section describes the operation of port 3.
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Operation of Port 3
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Port operation in output mode
• Setting a bit of the DDR3 register to "1" places the corresponding port pin in output mode.
• Data written to the PDR3 register in output mode is held in the output latch of the PDR and output to the
port pins.
• The PDR3 register can be accessed in read mode to read the value at the port pins (the same value as in
the output latch of the PDR).
Note:
If a read-modify-write instruction (such as an instruction that sets bits) is used with the port data
register, the target bits of the register are set to the specified value. The bits that have been
specified for output using the DDR register are not affected, but for the bits that have been specified
for input, a value input from the pins is written to the output latch and output as is. Before switching
the mode for the bits from input to output, therefore, write output data to the PDR register, then
specify output mode in the DDR register.
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Port operation in input mode
• Resetting a bit of the DDR3 register to "0" places the corresponding port pin in input mode.
• In input mode, the output buffer is turned off, and the pins are placed in a high impedance state.
• Data written to the PDR3 register in input mode is held in the output latch of the PDR but not output to
the port pins.
• The PDR3 register can be accessed in read mode to read the level value (0 or 1) at the port pins.
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Port operation for resource output
The resource output enable bit is set to enable the port to be used for resource output. The state of the
resource enable bit takes precedence when specifying a switch between input and output. Even if a DDR3
register bit is "0", the corresponding port pin is used for resource output if the resource has been enabled for
output. Because the value at the pins can be read even if resource output is enabled, the resource output
value can be read.
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Port operation after a reset
• When the CPU is reset, the DDR3 register is initialized to "0". As a result, the output buffer is turned
off (I/O mode changes to input), and the pins are placed in a high impedance state.
• The PDR3 register is not initialized when the CPU is reset. To use the port in output mode, therefore,
output mode must be specified in the DDR3 register after the output data is set in the PDR3 register.