Fujitsu MB90460 Series, Hardware Manual, Page: 316 / 739

297
CHAPTER 14 MULTI-FUNCTIONAL TIMER
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TImer Control Ctatus Register, Lower Byte (TCCSL)
Figure 14.4-9 Timer Control Status Register (TCCSL)
Address bit7 6 5 4 3 2 1 0 Initial value
00005E
H
BFE STOP MODE SCLR CLK2 CLK1 CLK0 -0100000
B
R/W R/W R/W R/W R/W R/W R/W R/W
CLK2 CLK1 CLK0
Clock frequency selection bit
Count
clock
φ
= 16 MHz
φ
= 8 MHz
φ
= 4 MHz
φ
= 1 MHz
0 0 0
φ
62.5 ns 125 ns 0.25
µ
s 1
µ
s
0 0 1
φ
/2
125 ns 0.25
µ
s 0.5
µ
s 2
µ
s
0 1 0
φ
/4 0.25
µ
s 0.5
µ
s 1
µ
s 4
µ
s
0 1 1
φ
/8 0.5
µ
s 1
µ
s 2
µ
s 8
µ
s
1 0 0
φ
/16 1
µ
s 2
µ
s 4
µ
s 16
µ
s
1 0 1
φ
/32 2
µ
s 4
µ
s 8
µ
s 32
µ
s
1 1 0
φ
/64 4
µ
s 8
µ
s 16
µ
s 64
µ
s
1 1 1
φ
/128 8
µ
s 16
µ
s 32
µ
s 128
µ
s
φ
: Machine cycle
SCLR
Timer clear bit
Write Read
0 Clear SCLR bit
Always read as ”0 ”
1
Initialize counter to “ 0000
H
”
MODE Timer counting mode
0 up-count mode
1 up-down count mode
STOP Timer enable bit
0 Counting is enabled (operation)
1 Counting is disabled (stop)
BFE Compare clear buffer enable bit
0
Disable compare clear buffer
1 Enable compare clear buffer
R/W : Read and write
: Initial value
— : Not used