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CHAPTER 15 MULTI-PULSE GENERATOR
Figure 15.1-2 PPG Falling Edge Synchronization
Note:
Switch from one PPG synchronization mode to another PPG synchronization mode (e.g. from rising-
edge synchronization to falling-edge synchronization or vice versa) is inhibited, no synchronization
mode must be the transit for such switch.
●
Input Position Detect Control
The input signal at the Multi-pulse Generator input pins (SNI2 to SNI0) is used to detect the rotor position
of the DC motor. There is a Noise Filter for all SNI2 to SNI0 input and Table 15.1-2 shows the noise width
for noise filter of SNI2 to SNI0 pins. The followings are conditions for the input position detect circuit:
•
3 edge selection for all SNI2 to SNI0; Rising edge, falling edge and both edges.
•
Compare the levels of SNI2 to SNI0 inputs with RDA2 to RDA0 bits of Output Data Register (OPDR:
RDA2 to RDA0).
After above condition met, the writing timing signal will be generated for the data transfer between
OPDBR registers and OPDR register.
Furthermore, the edge detection for individual input (SNI2 to SNI0) can be disable/enable.
OP4’
OP5’
OP4
OP5
PPG
Asynchronous State Change
Synchronous State Change
Sequencer changes
state due to, e.g. the
Glitch
reload timer 0 underflow.
WTS1,WTS0 = 00
B
WTS1,WTS0 = 10
B
Summary of Contents for MB90460 Series
Page 1: ...The following document contains information on Cypress products ...
Page 3: ......
Page 5: ......
Page 9: ...iv ...
Page 41: ...22 CHAPTER 1 OVERVIEW ...
Page 45: ...26 CHAPTER 2 NOTES ON HANDLING DEVICES ...
Page 83: ...64 CHAPTER 3 CPU ...
Page 95: ...76 CHAPTER 4 RESET ...
Page 107: ...88 CHAPTER 5 CLOCK ...
Page 131: ...112 CHAPTER 6 LOW POWER CONSUMPTION MODE ...
Page 175: ...156 CHAPTER 7 INTERRUPT ...
Page 181: ...162 CHAPTER 8 MODE SETTING ...
Page 223: ...204 CHAPTER 9 I O PORT ...
Page 237: ...218 CHAPTER 10 TIME BASE TIMER ...
Page 247: ...228 CHAPTER 11 WATCHDOG TIMER ...
Page 275: ...256 CHAPTER 12 16 BIT RELOAD TIMER ...
Page 373: ...354 CHAPTER 14 MULTI FUNCTIONAL TIMER ...
Page 485: ...466 CHAPTER 16 PWC Timer ...
Page 531: ...512 CHAPTER 17 UART ...
Page 559: ...540 CHAPTER 19 DELAYED INTERRUPT GENERATOR MODULE ...
Page 589: ...570 CHAPTER 20 8 10 BIT A D CONVERTER ...
Page 601: ...582 CHAPTER 21 ROM CORRECTION FUNCTION ...
Page 633: ...614 CHAPTER 23 512K 1024K BIT FLASH MEMORY ...
Page 645: ...626 CHAPTER 24 EXAMPLE OF F2 MC 16LX MB90F462 F462A F463A CONNECTION FOR SERIAL WRITING ...
Page 715: ...696 APPENDIX ...
Page 716: ...697 INDEX INDEX The index follows on the next page This is listed in alphabetic order ...
Page 739: ......