Fujitsu MB90460 Series, Hardware Manual, Page: 375 / 739

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CHAPTER 15 MULTI-PULSE GENERATOR
15.1 Overview of Multi-pulse Generator
The Multi-pulse Generator consists of a 16-bit PPG timer, a 16-bit reload timer and a
waveform sequencer. By using the waveform sequencer, 16-bit PPG timer output signal
can be directed to Multi-pulse Generator output (OPT5 to OPT0) according to the input
signal of Multi-pulse Generator (SNI2 to SNI0). Meanwhile, the OPT5 to OPT0 output
signal can be hardware terminated by DTTI1 input in case of emergency. The OPT5 to
OPT0 output signals are synchronized with the PPG signal in order to eliminate the
unwanted glitch.
Note:
In MB90465 series, 16-bit PPG timer and waveform sequencer are not present in
Multi-pulse Generator, but 16-bit Reload Timer can be used individually.
For the detail information about 16-bit Reload Timer and 16-bit PPG Timer, please refer
to Chapter 12, 16-bit Reload Timer and Chapter 13, 16-bit PPG Timer respectively.
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Function of Waveform Sequencer
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Output Signal Control
With waveform sequencer, it is possible to generate 16-bit PPG waveform output and DC chopper
waveform output at the Multi-pulse Generator output (OPT5 to OPT0).
• When an effective edge of the input signal from Multi-pulse Generator position detect input (SNI2 to
SNI0) or when the 16-bit reload timer is underflow or when the OPDBR0 register is written, one of
Output Data Buffer Registers (OPDBRB to OPDBR0) will be loaded into the Output Data Register
(OPDR).
• The Output Data Register (OPDR) determines the 16-bit PPG timer output to which OPT output (OPT5
to OPT0). By loading different Output Data Buffer Registers (OPDBRB to OPDBR0) into the Output
Data Register (OPDR). Various combination of OPT outputs (OPT5 to OPT0) can be obtained.
• Therefore, the 16-bit PPG timer output can be presented/absented at Multi-pulse Generator output
(OPT5 to OPT0) or switch the PPG timer output signal from one OPT output to another OPT output
according to the sequence set in the Output Data Register (OPDR) and 12 Output Data Buffer Registers
(OPDBRB to OPDBR0). Meanwhile, the 16-bit reload timer can insert a delay when switch OPT
output.
• Table 15.1-1 shows the combination the data transfer from OPDBRB to OPDBR0 registers to OPDR
register.
Table 15.1-1 Data Transfer from OPDBRB to OPDBR0 Registers to OPDR Register
Combination Data transfer from OPDBRB to OPDBR0 to OPDR
1 Data transfer from OPDBR0 to OPDR after OPDBR0 is written by software.
2 Triggered by the16-bit reload timer 0 underflow.
3 Triggered by the position detection input (SNI2 to SNI0).
4
Triggered by the 16-bit reload timer 0 underflow.
The 16-bit timer is started by the position detection comparison circuit.
5 Triggered either by the 16-bit reload timer 0 underflow, or by the position detection input.