Fujitsu MB90460 Series, Hardware Manual, Page: 460 / 739

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CHAPTER 16 PWC Timer
■
PWC control Status Register, Lower Byte (PWCSL0/PWCSL1)
Figure 16.4-3 PWC Control Status Register (PWCSL0/PWCSL1)
Address bit 7 6 5 4 3 2 1 0 Initial value
ch.0: 000008
H
ch.1: 000028
H
CKS1 CKS0
Reserved Reserved
S/C MOD2 MOD1 MOD0
00000000
B
R/W R/W R/W R/W R/W R/W R/W R/W
MOD2 MOD1 MOD0 Operation mode / count edge selection
0 0 0 Timer mode and no pulse output
0 0 1
Timer mode and pulse output (PWO pin valid):
reload mode only
0 1 0
All edge-to-edge pulse-width measurement
mode (rising edge or falling edge to falling edge
or rising edge)
0 1 1
Division period measurement mode
(when the input divider is used)
1 0 0
Rising edge-to-rising edge period measurement
mode (rising edge to rising edge)
1 0 1
H pulse-width measurement mode
(rising edge to falling edge)
1 1 0
L pulse-width measurement mode
(falling edge to rising edge)
1 1 1
Falling edge-to-falling edge period measurement
mode (falling edge to falling edge)
S/C
Count mode
selection
Timer mode
Pulse-width count
mode
0
Single
measurement mode
No reload (one shot)
Stop after one
measurement
1
Continuous
measurement mode
Reload
(reload timer)
Buffer register is
valid Continuous
measurement:
Buffer register is
valid
CKS1 CKS0 Count clock selection
0 0
Machine clock divided by 4
(0.25
µ
s for machine cycle at 16 MHz)
0 1
Machine clock divided by 16
(1.0
µ
s for machine cycle at 16 MHz)
1 0
Machine clock divided by 32
(2.0
µ
s for machine cycle at 16 MHz)
1 1 Setting prohibited (undefined)
X : Indeterminate
R/W : Read and write
: Initial value
— : Not used