Fujitsu MB90460 Series, Hardware Manual, Page: 72 / 739

53
CHAPTER 3 CPU
3.7.8 Direct Page Register (DPR)
The direct page register (DPR) is an 8-bit register that specifies bits 8 to 15 (addr8 to
addr15) of the operand address when a short direct addressing instruction is executed.
■
Direct Page Register (DPR)
As shown in Figure 3.7-14, the DPR specifies bits 8 to 15 (addr8 to addr15) of the operand address when a
short direct addressing instruction is executed. The DPR is 8-bits long. The DPR is initialized to 01
H
by a
reset. The DPR can be read and written using an instruction.
Figure 3.7-14 Physical Address Generation by the Direct Page Register (DPR)
Figure 3.7-15 shows an example of direct page register (DPR) setting and data access.
Figure 3.7-15 Example of Direct Page Register (DPR) Setting and Data Access
DTB register DDR register Direct address in instruction
αααααααα ββββββββ
γγγγγγγγ
ααααααααββββββββγγγγγγγγ
MSB LSB
24-bit physical address
DTB register
5A
H
MSB LSB
123458
H
123456
H
MOV S:56H, #5AH
Memory space
123454
H
Upper
8 bits
Lower
8 bits
DPR register
12
H
34
H
Instruction execution results